Uvm_hdl_deposit issue

Hi,

I have a small example where i try to deposit a value to a variable. but it doesnt seem to work? Can any tell me what is wrong here?



module xyz;
  reg [3:0] cfg;
endmodule

module bbq;
  xyz test();
endmodule

class basic_test extends uvm_test;

  `uvm_component_utils(basic_test)
  
 

  
  function new(string name = "basic_test",uvm_component parent=null);
    super.new(name,parent);
  endfunction : new

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    if (uvm_hdl_check_path ("tb.a.test.cfg"))
      `uvm_info ("TEST","Path tb.a.test.cfg exists", UVM_NONE); 
  endfunction : build_phase

  
  virtual function void end_of_elaboration();
   print();  
  endfunction 
  
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    if (!uvm_hdl_deposit ("tb.a.test.cfg",4'h8))
      `uvm_error ("TEST","Deposit failed for this path tb.a.test.cfg");
    phase.drop_objection(this);
  endtask
endclass : basic_test


module tb;
  bbq a();
  
   initial begin
    $dumpfile ("dump.vcd");
    $dumpvars (0,tb);
   
  end
  
  initial begin
    run_test("basic_test");
  end
  
 
   
endmodule

Error Message : 
UVM_ERROR: set: unable to write to hdl path (tb.a.test.cfg)
You may not have sufficient PLI/ACC capabilites enabled for that path
UVM_ERROR testbench.sv(39) @ 0: uvm_test_top [TEST] Deposit failed for this path tb.a.test.cfg

In reply to rag123:

Access to a signal via the PLI is a tool-related issue. Refer to your simulator documentation on how to enable PLI access to design signals.

In reply to cgales:

I am not sure if it is a tool issue. It seems i dont see the error message anymore. i dont know if the value is deposited.


import uvm_pkg::*;

class basic_test extends uvm_test;

  `uvm_component_utils(basic_test)
  
 

  
  function new(string name = "basic_test",uvm_component parent=null);
    super.new(name,parent);
  endfunction : new

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    if (uvm_hdl_check_path ("tb.a.test.cfg"))
      `uvm_info ("TEST","Path tb.a.test.cfg exists", UVM_NONE);
  
    
  endfunction : build_phase

  
  virtual function void end_of_elaboration();

    print();  
  endfunction 
  
  virtual task run_phase(uvm_phase phase);
   #1ns
    phase.raise_objection(this);
    #1ns
    if (!uvm_hdl_deposit ("tb.a.test.cfg",4'h8))
      `uvm_error ("TEST","Deposit failed for this path tb.a.test.cfg");
    
    #5ns 
    if (!uvm_hdl_deposit ("tb.a.test.cfg",4'h7))
      `uvm_error ("TEST","Deposit failed for this path tb.a.test.cfg");
    phase.drop_objection(this);
 
  endtask
endclass : basic_test


module tb;
  bbq a();
  
   
  
  initial run_test("basic_test");
  initial #3ns $monitor($time,,tb.a.test.cfg);  
  
  initial begin
  $display ("I am entering here");
  end
  initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, tb);
  end
 
   
endmodule

module xyz;
  reg [3:0] cfg;
endmodule

module bbq;
  xyz test();
endmodule

In reply to rag123:

You should insert some additional diagnostic messages. See the working code here:

import uvm_pkg::*;
`include "uvm_macros.svh"
 
class basic_test extends uvm_test;
 
  `uvm_component_utils(basic_test)
 
  function new(string name = "basic_test",uvm_component parent=null);
    super.new(name,parent);
  endfunction : new
 
  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
 
    if (uvm_hdl_check_path ("tb.a.test.cfg"))
      `uvm_info ("TEST","Path tb.a.test.cfg exists", UVM_NONE);
 
 
  endfunction : build_phase
 
  virtual task run_phase(uvm_phase phase);
    `uvm_info(get_type_name(), "Entering test run_phase", UVM_MEDIUM)
    phase.raise_objection(this);
    if (!uvm_hdl_deposit ("tb.a.test.cfg",4'h8))
      `uvm_error ("TEST","Deposit failed for this path tb.a.test.cfg");
    `uvm_info (get_type_name(),$sformatf("deposit = %0h", tb.a.test.cfg), UVM_NONE);
    #50ns 
    if (!uvm_hdl_deposit ("tb.a.test.cfg",4'h7))
      `uvm_error ("TEST","Deposit failed for this path tb.a.test.cfg");
    `uvm_info (get_type_name(),$sformatf("deposit = %0h", tb.a.test.cfg), UVM_NONE);
    phase.drop_objection(this);
 
  endtask
endclass : basic_test
 
 
module tb;
  bbq a();
 
 
 
  initial run_test("basic_test");

  initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, tb);
  end 
endmodule
 
module xyz;
  reg [3:0] cfg;
endmodule
 
module bbq;
  xyz test();
endmodule

In reply to chr_sue:

Thank you :)