I have a small example where i try to deposit a value to a variable. but it doesnt seem to work? Can any tell me what is wrong here?
module xyz;
reg [3:0] cfg;
endmodule
module bbq;
xyz test();
endmodule
class basic_test extends uvm_test;
`uvm_component_utils(basic_test)
function new(string name = "basic_test",uvm_component parent=null);
super.new(name,parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
if (uvm_hdl_check_path ("tb.a.test.cfg"))
`uvm_info ("TEST","Path tb.a.test.cfg exists", UVM_NONE);
endfunction : build_phase
virtual function void end_of_elaboration();
print();
endfunction
virtual task run_phase(uvm_phase phase);
phase.raise_objection(this);
if (!uvm_hdl_deposit ("tb.a.test.cfg",4'h8))
`uvm_error ("TEST","Deposit failed for this path tb.a.test.cfg");
phase.drop_objection(this);
endtask
endclass : basic_test
module tb;
bbq a();
initial begin
$dumpfile ("dump.vcd");
$dumpvars (0,tb);
end
initial begin
run_test("basic_test");
end
endmodule
Error Message :
UVM_ERROR: set: unable to write to hdl path (tb.a.test.cfg)
You may not have sufficient PLI/ACC capabilites enabled for that path
UVM_ERROR testbench.sv(39) @ 0: uvm_test_top [TEST] Deposit failed for this path tb.a.test.cfg