Uvm_hdl_deposit is behaving like uvm_hdl_force in NCSIM

UVM
,
1

Hi All,

uvm_hdl_deposit is behaving like uvm_hdl_force whenever I am depositing values on module internal wire signals.

FYI:

  1. The input signals are toggling like D, clk_enable.
  2. uvm_hdl_deposit placed on virtual sequence task body.
  3. using NCSIM tool.
  4. uvm 1.2 version.

please tell uvm_hdl_deposit use case. how to resolve the issue?

thanks
kbkdec15

2

In reply to Balu_15:

This might be a tool-related issue. Please talk to your tool-provider.