UVM_FATAL in Simulation

UVM
1

Hi folks,

Can anyone please help me with understanding below UVM_FATAL error in simulation.

UVM_FATAL /designware/S-2021.09-8/vip/svt/amba_svt/S-2021.12/axi_slave_svt/sverilog/src/vcs/svt_axi_base_slave_common.svp(5760) @ 14005ns: uvm_test_top.env.amba_system_env_0.axi_system[2].slave[4] [receive_write_addr] {OBJECT_NUM('d100000) PORT_ID('d4) PORT_NAME(slave[4]) TYPE(WRITE) COHERENT_XACT_TYPE(WRITENOSNOOP) ID('h4) SECURE('d1) ADDR('h60000000) CACHE_TYPE('d0) START_TIME(14005ns)} The object handle given to the sequencer by the monitor has not been returned back to the driver in 0 time. Please ensure that the sequence returns the object received from the monitor, back to the driver in 0 time.

Thanks,
Shipra

2

In reply to Shipra .:

Could you please give some more information about your UVM architecture. Do you have a connection between the sequencer and the monitor?.

3

In reply to chr_sue:

No , there is no connection between sequencer and monitor . This agent is in passive mode , only monitor is present.

4

In reply to Shipra .:

I’m refering to this line:
‘The object handle given to the sequencer by the monitor has not been returned back to the driver in 0 time.’
It seems there is a connection between the monitor and the sequencer. Are you trying to send a response from the monitor to a sequencer?

5

Seems like your response / slave sequence is not running