Hi,
I keep getting the following error while running the uvm_reg_bit_bash_seq:
Writing a 1 in bit #0 of register “abc_addr_map.abc_reg.ABC_N[41]” with initial value 'h0000000000000000 yielded 'h0000000000000000 instead of 'h0000000000000001
The similar error (but in different bit positions) occurs in several write/read cycles through the simulation, i.e. when a '1 is written into the register through the write() API of UVM RAL, ‘1’ is expected to be read back through the read() API of RAL but this does not seem to be the case. Strangely though there is no issue with the DUT, as observed from the wave dump. The write and read values from DUT both match. In fact, at the precise time of the error occurrence, as seen from the log, the value read from DUT is what is written into the DUT.
Why is it then that the log file is reporting the error? Is it an issue with the predictor/adaptor in the ENV? It appears that there is a delay of several cycles when the mirrored value is updated with the read value. At the time of the next error, the message goes as follows:
Writing a 1 in bit #1 of register “abc_addr_map.abc_reg.ABC_N[41]” with initial value 'h0000000000000001 yielded 'h0000000000000001 instead of 'h0000000000000003
As seen from above, the initial value has been updated with ‘1’, which should have been done during the previous read cycle. In this situation, the '1 written into bit #1 is expected to be read back as ‘3’ which is not case.
Please let me know what you think of this issue and how to go about resolving it. Would highly appreciate your timely and valuable inputs.
Thanks and Regards,
Ashwath