There is no issue, if I use “uvm_do_on”, but issue with “uvm_do_on_with”
Getting error as below…
`uvm_do_on_with(mem_abv,p_sequencer.memseqr,{req.addr >= 200;})
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ncsim: *E,RNDCNSTE (./mem_vseq.sv,44|71): Randomization constraint has this error, which will cause the randomize function to return 0 and no new rand values will be set:
Null handle references in constraints are not supported.
1030 NS + 5 (stop Randomize: Randomize failure)
What could be the issue??
How this constrains works??
Highest constraint override with lower constrains right?
I know this will work if I’m not using `uvm_do macro.
my point here is to report the `uvm_do macro issue.
interestingly, uvm_do_with macro constraint works only with local variable in seq.
Let say, I have local variable “add” in sequence which is getting assigned to req.addr with some constraint, which can able to constraint again from the higher level.
Is there going to be fix for those issues in recent times? Or uvm_macro meant for this for particular reasons?
In reply to tfitz:
Hi Tom,
I use the method you suggested, in my sequence, I a child sequence, I create/start it as below
ts_mb_seq = ts_mb_base_sequence_c::type_id::create("ts_mb_seq");
ts_mb_seq.randomize() with {req.crc24_error == FALSE;};
ts_mb_seq.start(p_sequencer.ts_mb_sequencer);
I got a run time randomization error with ncsim because of a Null ptr reference.
I understand that at this point, the req of the ts_mb_seq isn’t created yet. How can I get around this, or is this just a ncsim specific issue?
The error below. Thanks.
ts_mb_seq.randomize() with {req.crc24_error == FALSE;};
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ncsim: *E,RNDCNSTE (…/uvcs/plc_gen_uvc/src/sequences/plc_base_sequence.sv,110|42): Randomization constraint has this error, which will cause the randomize function to return 0 and no new rand values will be set:
Null handle references in constraints are not supported.
27670 NS + 29 (stop Randomize: Randomize failure)
The general issue here is you have a pair of layered/hierarchical sequences, and you are trying to randomize both the lower level sequence and sequence_item at the same time before the sequence_item (req) gets constructed. There are several approaches to solving this problem.
The reccomended OOP way of doing this is avoiding using the
randomizewith clause, which is not OOP friendly. Instead, use the factory to override whatever sequence_item class gets created by the lower level sequence with an extended class that adds the constraint you want.
Basically this is my pkt and I want to assign 0 value to a particular field according to ln_align_lost.
task ln_align_lost_fmt(bit [1:0] slice_idx, comlink_id);
bit [31:0] ln_align_lost;
`uvm_do_on_with(req,`hd7_cl_sequencer(slice_idx,comlink_id),
{ dll_frame_typ == NORMAL;
if(cla.is_present("-rx_ln_align_lost"))begin // this is command line switch, if I give it then only I want to assign value
ln_align_lost = $urandom_range(1,8);
if(ln_align_lost == 1)begin
fc1 = 0;
end else if(ln_align_lost == 2)begin
fc0 = 0;
end else if(ln_align_lost == 3)begin
ack_id = 0;
end else if(ln_align_lost == 4)begin
ack_valid = 0;
end else if(ln_align_lost == 5)begin
pkt_id = 0;
end else if(ln_align_lost == 6)begin
irp_pkt_typ = 0;
end else if(ln_align_lost == 7)begin
eop = 0;
end else if(ln_align_lost == 8)begin
sop = 0;
end
end
}
) // Getting error here
endtask
I am getting this error “illegal expression primary [4.2(IEEE)].)”