Uvm_config_db:set method does not work

UVM
1

questasim command to run below program:
//vlog -sv +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv $UVM_HOME/src/dpi/uvm_dpi.cc uvm_object_cfg_example.sv
//vsim -c tb_top -l simv.log -do “run -all;quit” +UVM_TESTNAME=test

Program:

import uvm_pkg::*;

`include “uvm_macros.svh”

class address_map_info extends uvm_object;

rand int min_addr;
rand int max_addr;

function new(string name = “address_map_info”);
super.new(name);
endfunction

uvm_object_utils_begin(address_map_info) uvm_field_int(min_addr, UVM_DEFAULT)
uvm_field_int(max_addr, UVM_DEFAULT) uvm_object_utils_end

endclass : address_map_info

class test extends uvm_test;
`uvm_component_utils(test)

address_map_info cfg;

function new(string name=“test”,uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
super.build_phase(phase);
cfg = address_map_info::type_id::create(“cfg”, this);
uvm_config_db#(int)::set(this,“.cfg",“min_addr”,25);
uvm_config_db#(int)::set(this,".cfg”,“max_addr”,30);
endfunction

task run_phase(uvm_phase phase);
phase.phase_done.set_drain_time(this, 50);
fork
begin
phase.raise_objection(this, “Starting run phase - raising objection”);
#2000;
phase.drop_objection(this, “Stopping run phase through drop_objection”);
end

begin
#5;
uvm_info("TEST",$sformatf("::min_addr %0d max_addr %0d",cfg.min_addr,cfg.max_addr),UVM_NONE) cfg.randomize(); #5; uvm_info(“TEST”,$sformatf(“::min_addr %0d max_addr %0d”,cfg.min_addr,cfg.max_addr),UVM_NONE)
end
join
endtask

endclass

module tb_top;
initial begin
run_test();
end
endmodule

Output:

UVM_INFO @ 0: reporter [RNTST] Running test test…

UVM_INFO xyz(48) @ 5: uvm_test_top [TEST] ::min_addr 0 max_addr 0

UVM_INFO xyz(51) @ 10: uvm_test_top [TEST] ::min_addr 621151839 max_addr -460094641

address_map_info is typedef of uvm_object. Using set (of uvm_config_db) method it sets value of two integers min_addr,max_addr. When these two variables are displayed in run_phase, values of these two variables after randomizing looks ok but, values of these two variables are unlikely zero after delay of #5 instead of 25,30.

I dont understand why does this happen?
Can anybody have fix in this code,It will really helpful for me?

Thanks,
Urvish

2

Do not use the field automation macros. Among many other things, they do not call get_config automatically other than in the build phase of an uvm_component. Also `uvm_field_int does not map to uvm_config_db#(int) even if this was a component. You would have needed to use uvm_config_db#(uvm_bitstream_t).

A better solution is to it directly

cfg.min_addr = 25;
cfg.max_addr = 30;

And then put cgf in you config data base.

See MacroCostBenefit | Verification Academy
and
Configuration | Verification Academy

3

In reply to dave_59:

Thanks Dave for your help and link. Got your point.

4

In reply to Urvish_69:

Dave,

Can we access the config variables in transaction item class extended from uvm_sequence_item?

Thanks,
Urvish

5

In reply to Urvish_69:

You can use the same mechanisms described here for sequences for sequence items.