Could anyone explain the need for uvm_cmdline_processor when we can use $value$plusargs or $test$plusargs?
In reply to ManjunathBhat:
Just like many things in the UVM, (uvm_queue, uvm_event),someone though they could pack more features than what was already standard in SystemVerilog.
But the thing in the uvm_cmdline_processor that it really useful is the ability to have multiple plusargs with the same name, as given in the reference manual:
+foo=1,yes,on +foo=5,no,off
$value$plusargs does not let you do this, which is very handy for the UVM options
+uvm_set_type_override=A_class,B_class +uvm_set_type_override=C_class,D_class