Q1 in uvm in which class we can write checker.
Q2 what is difference between assertion and checker.
In reply to Henriques:
A SystemVerilog checker is a construct similar to a module, with several additional limitations.
You can not instantiate a checker inside of a class object, therefor you can not use a checker within your UVM test/environment.
Refer to Chapter 17 of the IEEE SystemVerilog Language Standard for the definition and usage of a checker.