Hi,
I have existing SystemC design I am trying to drive from SV side of my uvmc testbench. My problem is such that on SC (design) side of connections it is expected the transactions (tlm_generic_payload) include handle to memory manager (nb_transport_fw, trans.acquire() called on arrival). However, uvmc does not provide such by default.
I have been trying to redefine converter for generic payload, so I could provide the needed memory manager from converter level (do_unpack). However, everything seems to be static by nature and I have not been able to find a spot where I could add the memory management object in a consistent manner.
How have you planned the case where design expects memory manager handle from incoming transactions?
Thanks.