UVMC binding error

UVM
,
1

I am facing some difficulties in UVM connect library. I have connected TLM port on both SV and SystemC side using uvmc_tlm::connect(…) (look for apb_socket) but still getting the below error:

Loading /prj/qct/virtualplatform/blr_virtualplatform01/rjindal/verification/spi_uvm_sysc_env/tb_build/block_level_tbs/spi_tb/sim/work/_sc/linux_gcc-4.7.4/systemc.so

Loading /prj/qct/virtualplatform/blr_virtualplatform01/rjindal/verification/spi_uvm_sysc_env/tb_build/block_level_tbs/spi_tb/sim/work.sc_main

Connecting an SC-side proxy port for ‘sc_main/env/spi_inst/apb_socket’ with lookup string ‘apb_socket’ for later connection with SV

Connecting an SC-side proxy chan for ‘sc_main/env/spi_inst/spi_socket’ with lookup string ‘spi_socket’ for later connection with SV

run -all

UVMC Error: Cannot find binding for port registered with names

----------------------------------------------------------------

Registering SV-side ‘uvm_test_top.m_env.m_scoreboard.out’ and lookup string ‘apb_socket’ for later connection with SC

UVMC-Error: No SC-side port/export/interface registered with name=uvm_test_top.m_env.m_scoreboard.out or lookup=apb_socket. (sv_mask=7 sv_id=1)

Registered SC-side UVMC proxies are:

UVM_FATAL @ 0: reporter [BUILDERR] stopping due to build errors

can you please tell me what can be the issue here ?

2

In reply to r7jindal:

The UVMC-Error is showing you the reason. You should dig into your Details. Without seeing more code I cannot give you any advice.

3

In reply to chr_sue:

Thanks , I am able to fix it. Do you have any converter example with SystemC as producer using UVMC APIs. In UVMC package I am able to find SV producer example only.

4

In reply to r7jindal:

I have my own view about using UVMC. SystemC does not have the capabilities SystemVerilog has. For this reason my recommendation is to use only SC methods in an UVM testbench. The best place or case is to use refernece models implemented in SC.
If you are using an UVM-Framework Generator a whole UVM Environment will be generated in a few hours. With the UVM Environment you have the full power of SV/UVM for your verifcation.
UVM Fremaework Generators ar eavailable free-of-charge like the EasierUVM Framework Genereator from Doulos (see Doulos KnowHow), UVMF from Mentor or any of the numerous Generators from other companies or freelancers. See also my Generator (www.christoph-suehnel.de).
Hope this gives you a better understanding.

5

In reply to r7jindal:

In reply to chr_sue:
Thanks , I am able to fix it. Do you have any converter example with SystemC as producer using UVMC APIs. In UVMC package I am able to find SV producer example only.

Can you briefly explain the root cause and the fix for this issue?