Is uvm_analysis_port uvm_tlm_anamysis_fifo extend from uvm_component in the end?

UVM
1

as title

2

In reply to designer007:

You can see the inheritance in the UVM Reference Manual.

uvm_analysis_port

is extended from uvm_port_base and

uvm_tlm_analysis_fifo

is extended from uvm_tlm_fifo.

3

In reply to designer007:

as title

They are not, you cant have any phases in your port/fifo…

4

In reply to VE:

analysis port/fifo have any relationship with uvm_object or uvm_component.
if there are not extends from uvm_component,
is it correct thatbut analysis port/fifo are always exist as driver, not disappear like sequence.

5

In reply to designer007:

The fifo and ports/exports do not have arelationship with components.
But they are behaving like a component becaus they are belonging to the testbench. They will be created at runtime 0 and exist until the end of the simulation.