I have this code below for a testbench, it fails to execute the sequence. It only executes this statement
`uvm_info(“connect the sequence to the sequencer before”, “”, UVM_LOW) in adder_model_test. Why does the simulation hang and what debug techniques I can use to figure out what went wrong?? Please help.
// Code your design here
interface intf (input reset, input clk) ;
logic [31:0] a, b, c ;
endinterface
module adder (intf intf0) ;
assign intf0.c = intf0.a + intf0.b ;
endmodule
// Code your testbench here
// or browse Examples
import uvm_pkg::*;
module top_test ;
bit clk, reset ;
initial begin
#0 reset = 1’b1 ;
#1000 reset = 1’b0 ;
end
initial begin
clk = 1’b0 ;
forever #50 clk = ~clk ;
end
//initial begin
//`uvm_info($sformatf("%0d", $time), "Welcome to UVM", UVM_LOW) ;
//$display("this is just a test") ;
//#100000 $finish(2) ;
//end
intf intf0 (reset, clk) ;
adder adder_0 (intf0) ;
//register the interface in config DB
initial begin
uvm_config_db#(virtual intf)::set(uvm_root::get(),“*”,“vif”,intf0);
end
initial begin
run_test(“adder_model_test”);
end
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Code your design here
class uvm_add_item extends uvm_sequence_item ;
rand logic [31:0] a, b ;
//Utility and Field macros,
uvm_object_utils_begin(uvm_add_item) uvm_field_int(a,UVM_ALL_ON)
uvm_field_int(b,UVM_ALL_ON) uvm_object_utils_end
//call constructor
function new (string name = “uvm_add_item”) ;
super.new(name) ;
endfunction
constraint var_a { a < 32’h6; }
constraint var_b { b < 32’h4; }
endclass
class adder_sequencer extends uvm_sequencer #(uvm_add_item);
`uvm_component_utils(adder_sequencer)
//constructor
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
endclass
class uvm_sequence_add extends uvm_sequence #(uvm_add_item) ;
//uvm_sequence_utils(uvm_sequence_add, add_sequencer) uvm_object_utils(uvm_sequence_add)
//Constructor
function new(string name = “uvm_sequence_add”);
super.new(name);
endfunction
virtual task body();
uvm_add_item req ;
$display("At atage 1 \n") ;
`uvm_info("At stage 1", "", UVM_LOW)
req = uvm_add_item::type_id::create("req");
wait_for_grant();
`uvm_info("At stage 2", "", UVM_LOW)
if(!req.randomize()) `uvm_fatal("Could not randomize sequence", "")
else begin
send_request(req);
`uvm_info("At stage 3", "", UVM_LOW)
wait_for_item_done();
`uvm_info("At stage 4", "", UVM_LOW)
end
endtask
endclass
///////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////
class adder_driver extends uvm_driver #(uvm_add_item);
// Virtual Interface
virtual intf vif;
`uvm_component_utils(adder_driver)
//uvm_analysis_port #(mem_seq_item) Drvr2Sb_port;
// Constructor
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual intf)::get(this, “”, “vif”, vif))
`uvm_fatal(“NO_VIF”,{“virtual interface must be set for:”,get_full_name(),“.vif”});
endfunction: build_phase
// run phase
virtual task run_phase(uvm_phase phase);
forever begin
seq_item_port.get_next_item(req);
//respond_to_transfer(req);
drive();
seq_item_port.item_done();
end
endtask : run_phase
// drive
virtual task drive();
req.print();
@(negedge vif.clk) ;
vif.a <= req.a ;
vif.b <= req.b ;
`uvm_info(“Driver executed”, “”, UVM_LOW);
endtask : drive
endclass : adder_driver
class adder_monitor extends uvm_monitor;
`uvm_component_utils(adder_monitor)
// Virtual Interface
virtual intf vif;
uvm_analysis_port #(uvm_add_item) item_collected_port;
// Placeholder to capture transaction information.
uvm_add_item trans_collected;
// new - constructor
function new (string name, uvm_component parent);
super.new(name, parent);
trans_collected = new();
item_collected_port = new(“item_collected_port”, this);
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual intf)::get(this, “”, “vif”, vif))
`uvm_fatal(“NOVIF”,{“virtual interface must be set for: “,get_full_name(),”.vif”});
endfunction: build_phase
// run phase
virtual task run_phase(uvm_phase phase);
forever begin
end
endtask : run_phase
endclass : adder_monitor
class adder_agent extends uvm_agent;
// UVM automation macros for general components
`uvm_component_utils(adder_agent)
//declaring agent components
adder_driver driver;
adder_sequencer sequencer;
adder_monitor monitor;
// constructor
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
// build_phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(get_is_active() == UVM_ACTIVE) begin
driver = adder_driver::type_id::create("driver", this);
sequencer = adder_sequencer::type_id::create("sequencer", this);
end
monitor = adder_monitor::type_id::create("monitor", this);
endfunction : build_phase
// connect_phase
function void connect_phase(uvm_phase phase);
if(get_is_active() == UVM_ACTIVE) begin
driver.seq_item_port.connect(sequencer.seq_item_export);
end
endfunction : connect_phase
endclass : adder_agent
class adder_scoreboard extends uvm_scoreboard;
`uvm_component_utils(adder_scoreboard)
uvm_analysis_imp#(uvm_add_item, adder_scoreboard) item_collected_export;
// new - constructor
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
item_collected_export = new(“item_collected_export”, this);
endfunction: build_phase
// write
virtual function void write(uvm_add_item pkt);
$display(“SCB:: Pkt recived”);
pkt.print();
endfunction : write
// run phase
virtual task run_phase(uvm_phase phase);
endtask : run_phase
endclass : adder_scoreboard
class adder_model_env extends uvm_env;
`uvm_component_utils(adder_model_env)
//---------------------------------------
// agent and scoreboard instance
//---------------------------------------
adder_agent adder_agnt;
adder_scoreboard adder_scb;
//---------------------------------------
// constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
//---------------------------------------
// build_phase - crate the components
//---------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
adder_agnt = adder_agent::type_id::create("adder_agnt", this);
adder_scb = adder_scoreboard::type_id::create("adder_scb", this);
endfunction : build_phase
//---------------------------------------
// connect_phase - connecting monitor and scoreboard port
//---------------------------------------
function void connect_phase(uvm_phase phase);
adder_agnt.monitor.item_collected_port.connect(adder_scb.item_collected_export);
endfunction : connect_phase
endclass : adder_model_env
class adder_model_test extends uvm_test;
`uvm_component_utils(adder_model_test)
adder_model_env env;
uvm_sequence_add seq;
function new(string name = “adder_model_test”,uvm_component parent=null);
super.new(name,parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = adder_model_env::type_id::create("env", this);
seq = uvm_sequence_add::type_id::create("seq");
endfunction : build_phase
task run_phase(uvm_phase phase);
phase.raise_objection(this);
uvm_info("connect the sequence to the sequencer before", "", UVM_LOW) seq.start(env.adder_agnt.sequencer); uvm_info(“connect the sequence to the sequencer later”, “”, UVM_LOW)
phase.drop_objection(this);
endtask : run_phase
endclass : adder_model_test