UVM test failed

Hello,
I am new to UVM and I tried forming the testbench for an ALU DUT. Some of my results are getting “Test Pass” and some are getting “Failed”. For example, I performed an ‘AND’ function between two operands A and B, sometimes, it gives me a “Test Pass” and sometimes, “Failed”. I am confused what went wrong.
I am attaching the link to my playground, any help will be appreciated.

Thanks

In reply to SV26:

Looks like your DUT or your scoreboard is wrong.

In reply to chr_sue:

I tried changing the scoreboard, but still having the same problem. My DUT is working fine as I checked it with the modelsim and forced the same values for which the EDA-playground showed me “TEST FAILED”.

In reply to SV26:

2 things are responsible for your fail:
(1) you were not synchronizing on your clocking block and you did not send a copy of your collected transaction to the scoreboard.
See here the working examole:

I was excluding the clocking block and the modports for driver and monitor.

In reply to chr_sue:

Sir,
Thankyou so much for your response, but when I ran your working code,one of the test was still failing.

In your base_sequence, you have given normal randomization and it is not generating the sel = 3’b10
so create a separate sequence for sel = 3’b10 and check once.

I added the seq for sel = 3’b10 in sequence.sv .check once,now it is not getting test failed info.

In your design file, you have taken A, B and result all are the same lengths
if a = 4’b1111
b= 4’b’1111
sel = 3’b000

result = 5’b11110
change the result size.