Uvm in systemC

hello…
i am working on a project related to uvm in systemC. i would be glad to use some help to code in uvm in systemC since i am a bit new to this. thank you

In reply to vishwesh:

You will need to explain more about what you need assistance with. Do you want to use a SystemC design with a UVM testbench? Migrate from SystemC to UVM?

There are many different ways to interpret what you wrote and you didn’t ask any specific questions.

In reply to cgales:

Thanks for the answer.
To be precise, i need to code 4 to 1 multiplexer uvm testbench using the systemC. That means basically i need uvm testbench to be written in systemC.
Thank you.

In reply to vishwesh:
The UVM library exists as a standard for writing testbenches in SystemVerilog. A proof-of-concept UVM-SystemC library was released for review over a year ago, and there has been no further activity since that release. I suspect to use it, you will have to already know SystemC and some SystemVerilog UVM as there is no other information on it other than what is on the Accellera FAQ page.

In reply to vishwesh:

I’ve created uvm testbench using SystemC library from Accellera that Dave has mentioned above. Take a look at it! github.com/mayur13/SystemC/tree/master/projects/sc_testbench

In reply to MayurKubavat:

Hi Mayur,

I am new in UVM-systemc. I know systemc. Can you suggest me how to write a simple code of “AND” operation in UVM-systemc?

Thanks,
Prasenjit

In reply to vishwesh:

The UVM is a SystemVerilog base-class library and not a SystemC library. But you Can integrate SystemC components and objects into a UVM testbench using UVM-Connect. UVM-Connect is not part of the UVM.
BTW it does not make any sense to write a UVM TB for multiplexer.