UVM Seqeunce structure

UVM
,
1

Can someone suggest alternative coding styles for constraining randomized sequence variables from test for the scenario shown below.
The problem I have in current snippet is that though seq1 has no use for var1 it is merely used as placeholder to pass it on to seq2 as the test can’t directly start seq2. Also I want o pass var1 only for specific test scenario so I need to add constraint to make var1 =0 for other test cases.seq1 and seq2 have different parents so I cant use the common parent class to store var1.
One solution could be to use uvm_config_db and pass the var1 from test and get it directly from seq2. Any alternative suggestions?

class test1 extends base_test
..
..

int var1;
seq1 seq1_h;

task run_phase()
  if(!$test$plusargs("var=%d",var1))
    var1 = 0;

seq1_h = seq1::type_id::create("seq1_h");

if(var1 !=0)
seq1_h.var1_c.constraint_mode(0);
assert (seq1_h.randomize() with {
        ..
        ..
        var1 = var1;
       })
else 
  `uvm_fatal("Couldn't randomize");


endtask

endclass

class seq1 extends base_seq1;

rand int var1;

seq2 seq2_h;

constraint var1_c { var1 == 'h0;}

task body();
  seq2_h = seq2::type_id::create("seq2_h");
  
  assert (seq2_h.randomize() with {
             var1 == var1;
             ..
             ..
                       
           })
  else 
   `uvm_fatal("Couldn't randomize");

endtask

endclass
2

In reply to venkstart:

Try using $test$plusargs inside pre_randomize task of base sequence class.

function void pre_randomize;
if(!$test$plusargs(“var=%d”,var1))
var1 = 0;
// Rand_mode calls or constraint_mode calls
endfunction[/i][/i]

In test1 run_phase inline constraints, var1 = var1 was there instead of var1 == var1. And one more suggestion is, add a suffix to var1. Few simulators have abnormal behavior when inline vars and assigned vars are with same name.

Thanks.