In reply to Mustafa:
UVM_ERROR verilog_src/uvm-1.1d/src/reg/sequences/uvm_reg_bit_bash_seq.svh(175): rgm_seq.reg_single_bit_bash_seq [uvm_reg_bit_bash_seq] Writing a 0 in bit #0 of register "spi_rm.reg_0x0" with initial value 'h0000000000000001 yielded 'h0000000000000000 instead of 'h0000000000000001
Only reason sequence throwing message if reg_0x0 bit#0 is RO. Check it in your simulation and regfile if bit#0 is RO.
Sometime back my team also used to get such error, finally we found that access_type in regfile is different than what it was in DUT.
BTW, please use code tags for better reading :)