UVM register model: strange uvm_error message

UVM
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1

Hello,
I get the following error when running the sequence uvm_reg_bit_bash_seq
UVM_ERROR verilog_src/uvm-1.1d/src/reg/sequences/uvm_reg_bit_bash_seq.svh(175): rgm_seq.reg_single_bit_bash_seq [uvm_reg_bit_bash_seq] Writing a 0 in bit #0 of register “spi_rm.reg_0x0” with initial value 'h0000000000000001 yielded 'h0000000000000000 instead of 'h0000000000000001

The message states a correct action, writing 0 in bit #0 with initial value 'h01 yielded 'h00. So why does the sequence expect the value to be 'h01 instead of the correct one, which is 'h00 ?

Thanks

2

In reply to Mustafa:

Are you sure the field isn’t declared as read-only?

3

In reply to Tudor Timi:

Yes, I’m sure
By the way for “RO” fields a message similar to this may be displayed normally, but as an uvm_info not uvm_error as in my case.
i.e a an observed write transaction followed by an observed read transaction with no value change
In my case, the uvm_error message itself has contradiction

4

In reply to Mustafa:

The problem is for all “RW” fields
Another example:
UVM_ERROR verilog_src/uvm-1.1d/src/reg/sequences/uvm_reg_bit_bash_seq.svh(175) @ 143600000000: rgm_seq.reg_single_bit_bash_seq [uvm_reg_bit_bash_seq] Writing a 1 in bit #1 of register “spi_rm.reg_0x27” with initial value 'h0000000000000020 yielded 'h0000000000000022 instead of 'h0000000000000020

What is stated is correct, so why does it consider it as an error?

5

In reply to Mustafa:

@Mustafa,

UVM_ERROR verilog_src/uvm-1.1d/src/reg/sequences/uvm_reg_bit_bash_seq.svh(175): rgm_seq.reg_single_bit_bash_seq [uvm_reg_bit_bash_seq] Writing a 0 in bit #0 of register "spi_rm.reg_0x0" with initial value 'h0000000000000001 yielded 'h0000000000000000 instead of 'h0000000000000001

Only reason sequence throwing message if reg_0x0 bit#0 is RO. Check it in your simulation and regfile if bit#0 is RO.

Sometime back my team also used to get such error, finally we found that access_type in regfile is different than what it was in DUT.

BTW, please use code tags for better reading :)

6

In reply to Vinay Jain:

Hi Vinay Jain,
I appreciate it if we investigate the message again.
It says:

writing 0 in bit #0 of a register with initial value 'h01 yielded 'h00

which means in the RTL, the register is RW.
I’ve checked the register classes and made sure the field is defined as “RW”. Actually the whole register’s fields are defined as “RW”. So why the sequence expects the result to be 'h01 instead of the correct one 'h00 !

Thanks

7

In reply to Mustafa:

Hi Mustafa,

Did you find solution for this issue ?

Because I am also facing same issue. The field is RW, even though it is giving such error.

Regards,
Dhaval