UVM Register Model with mixed width registers

UVM
1

Hi,
I’m struggling with something in my UVM register model. I’m fairly new to UVM, so likely overlooking something easy.

The situation is this: I have a 64-bit AHB interface to my registers. The registers are a mixture of 64-bit wide registers, and 32-bit wide registers. The 32-bit wide registers are on 4 byte address boundaries, and the 64-bit registers are on 8 byte address boundaries. I have set up my register model specifying the size of the individual registers, told it the interface is 64 bits, and set up my address map. However, whenever I try to access a 32 bit register on a 4 byte address boundary, I get errors in my bus agent. I have tried using both 4 and 8 bytes in the create_map call, no difference in behaviour.

I’ve read that the register layer will handle cases like a 32-bit bus being used to access 64-bit data by issuing 2 transactions. I have the reverse problem, I only need half my 64-bit bus sometimes, and all of it other times. Is this behaviour already part of the UVM register layer, or is this custom behaviour I’ll have to add?

Thanks,

Dave

2

In reply to dbrown123:

My recommendation is you should use two different address maps, one for the 64-bit registers and another one with the 32 bit registers.
In my understanding it is impossible to handle both in thes ame address map.

3

In reply to dbrown123:

Just to update, I was able to solve this issue. I was using a 3rd party Verification IP, and I went in and modified their reg2bus and bus2reg functions to get the desired behaviour.

After figuring out the solution, I then learned that they have already added this feature in a newer version of the IP, so I could have saved some time if I were just using the latest.

So mixing 32 and 64 bit registers in a single address map is working great for me now.

Dave

4

In reply to dbrown123:

I have the same issue using 3rd party IP,
For 64 bit submaps the create_map is set to 8 bytes however the top reg map sets the n_bytes to 4,
On a 64 bit wide bus we shouldn’t expect two transactions for a 64 bit wide register right ?
Can you share what you fixed in the reg adapter to fix the problem ?

5

In reply to pavankumark10:

Pavan, when you use 8 bytes map, you need conditional transaction fields updates in your adapter. Something like below,
for example for AXI,
transfer.addr = rw.addr;
if (rw.n_bits == 64) begin
transfer.length = 1;
transfer.data = new[2];
end else begin
transfer.length = 0;
transfer.data = new[1];
end
Please let me know if this works. Thank you.

Thank you,
Mega

6

In reply to megamind:

Also response provided by chr_sue makes sense, where you can conditionally fetch the required map to drive transactions, but again you will need condition in your adapter at least for one of the case where register is 64 bit and you are using 8 byte interface.