I'm having an issue while using a UVM register model with an APB register adapter. I can post some code if required, but I think in this case it'll be clearer if I just explain the problem:
If a sequence issues a frontdoor register read on the same clock edge as the DUT updates the register internally, then the read value returned over apb is the 'old' value as expected, while the register now holds the new value. This is fine, and the scoreboard anticipates this update and does a backdoor predict of kind UVM_PREDICT_WRITE.
However, the register model read function also performs a predict one cycle later, using the value which was just read. This reverts the newly updated mirrored value back to the old value, so now the register model is out of sync with the DUT.
I've had a look through the UVM code and can't find a way to issue a frontdoor read access without it being followed by a prediction.
Does anyone here have any suggestions to get round this? I'd rather not avoid this occurrence altogether, as these sort of accesses are a genuine use case for the component.