In reply to Vinay Jain:
You are referring to an earlier version of our product IDesignSpec. I'm happy to say that the speed has improved significantly over the years.
Also, generation time is a small factor compared to the time spent in design/verification. So some additional questions that need to be considered are:
1. How comprehensive and customizable is the generated UVM model? Are coverage, constraints, HDL_PATHs properly handled? What about indirect registers, lock, shadow, alias, alternate register, interrupts, counters, FIFOs, wider registers, atomic registers, register arrays, etc.
2. Often tools do not generate RTL completely or there isn't enough flexibility to control the generated Verilog/VHDL - like CDC logic, pipeline delays, multiple bus domains, low-power, clock gating, special registers etc.
3. Other factors to consider are: Ease of use, ability to import legacy data, other generated artifacts like C/C++ API, complete UVM environment, documentation, responsiveness of support etc.
Register generators have evolved over the years. Its not just a register generator anymore, but a complete ESL tool which allows you to describe the complete Hardware/Software Interface (HSI) at a higher abstraction level.
Ultimately, you get what you pay for. You might get a free tool from a vendor, or create something fast in-house, but sooner or later it will be limiting and may cost you more.