How can we skip testing a register while using built in register test sequence from the TEST?
Where do we use “DO_NOT_TEST” attribute ?
In reply to debashis_paul:
Please check: Registers | Verification Academy
Registers and memories can be opted out of these auto tests by setting an individual “DO_NOT_TEST” attribute which isvchecked by the automatic sequence as runs. An example of where such an attribute would be used is a clock control register where writing random bits to it will actually stop the clock and cause all further DUT operations to fail.
Note that any of the automatic tests can be disabled for a given register or memory by the NO_REG_TEST attribute, or for memories by the NO_MEM_TEST attribute.
Setting An Attribute
In order to set an auto-test disable attribute on a register, you will need to use the UVM resource_db to set a bit with the attribute string, giving the path to the register or the memory as the scope variable. Since the UVM resource database is used, the attributes can be set from anywhere in the test bench at any time. However, the recommended approach is to set the attributes as part of the register model, this will most likely be done by specifying the attribute via the register model generators specification input file.
The following code excerpt shows how attributes would be implemented in a register model.
// From the build() method of the memory sub-system (mem_ss) block:
function void build();
//
// .....
//
// Example use of "dont_test" attributes:
// Stops mem_1_offset reset test
uvm_resource_db #(bit)::set({"REG::", this.mem_1_offset.get_full_name()}, "NO_REG_HW_RESET_TEST", 1);
// Stops mem_1_offset bit-bash test
uvm_resource_db #(bit)::set({"REG::", this.mem_1_offset.get_full_name()}, "NO_REG_BIT_BASH_TEST", 1);
// Stops mem_1 being tested with the walking auto test
uvm_resource_db #(bit)::set({"REG::", this.mem_1.get_full_name()}, "NO_MEM_WALK_TEST", 1); lock_model();
endfunction: build
This shows how the same could be achieved from a sequence:
//
// From within a sequence where the mem_ss_rm handle is set in the base_class:
//
task body; super.body();
// Disable mem_2 walking auto test
uvm_resource_db #(bit)::set({"REG::", mem_ss_rm.mem_1.get_full_name()}, "NO_MEM_WALK_TEST", 1);
//
// ...
//
endtask: body
Note that once an attribute has been set in the UVM resource database, it cannot be ‘unset’. This means that successiveuses of different levels of disabling within sequences may produce unwanted accumulative effects.
In reply to Lina.Lin:
In reply to debashis_paul:
Please check: Register Package | UVM Cookbook
Registers and memories can be opted out of these auto tests by setting an individual “DO_NOT_TEST” attribute which isvchecked by the automatic sequence as runs. An example of where such an attribute would be used is a clock control register where writing random bits to it will actually stop the clock and cause all further DUT operations to fail.
Note that any of the automatic tests can be disabled for a given register or memory by the NO_REG_TEST attribute, or for memories by the NO_MEM_TEST attribute.
Setting An Attribute
In order to set an auto-test disable attribute on a register, you will need to use the UVM resource_db to set a bit with the attribute string, giving the path to the register or the memory as the scope variable. Since the UVM resource database is used, the attributes can be set from anywhere in the test bench at any time. However, the recommended approach is to set the attributes as part of the register model, this will most likely be done by specifying the attribute via the register model generators specification input file.
The following code excerpt shows how attributes would be implemented in a register model.
// From the build() method of the memory sub-system (mem_ss) block:
function void build();
//
// .....
//
// Example use of "dont_test" attributes:
// Stops mem_1_offset reset test
uvm_resource_db #(bit)::set({"REG::", this.mem_1_offset.get_full_name()}, "NO_REG_HW_RESET_TEST", 1);
// Stops mem_1_offset bit-bash test
uvm_resource_db #(bit)::set({"REG::", this.mem_1_offset.get_full_name()}, "NO_REG_BIT_BASH_TEST", 1);
// Stops mem_1 being tested with the walking auto test
uvm_resource_db #(bit)::set({"REG::", this.mem_1.get_full_name()}, "NO_MEM_WALK_TEST", 1); lock_model();
endfunction: build
This shows how the same could be achieved from a sequence:
//
// From within a sequence where the mem_ss_rm handle is set in the base_class:
//
task body; super.body();
// Disable mem_2 walking auto test
uvm_resource_db #(bit)::set({"REG::", mem_ss_rm.mem_1.get_full_name()}, "NO_MEM_WALK_TEST", 1);
//
// ...
//
endtask: body
Note that once an attribute has been set in the UVM resource database, it cannot be ‘unset’. This means that successiveuses of different levels of disabling within sequences may produce unwanted accumulative effects.
thank you, I could execute it with ease.
In reply to Lina.Lin:
Suppose my Reg Block is associated with multiple maps. Can we restrict the built in sequence to test it using only a particular map?
How do we do if yes?
Thanks in advance
In reply to debashis_paul:
My understanding to the auto-test disable attribute of built-in auto-test sequences is set per register basis.If you want to test only one particular reg map in a reg block, you may consider to implement some user code like below to disable the other register maps’s auto-test. Code here is as an example, probably not very accurate, FYI.
//blk: reg model
//map_index[$]; the register map index array to hold the map id not to be tested
//attribute_name[$]: auto-test disable attribute array
function void set_attribute(uvm_reg_block blk, int map_index[$], string attribute_name[$]);
uvm_reg_map maps[$];
blk.get_maps(maps);
// Iterate over all maps defined for the RegModel block
foreach (maps[d]) begin
uvm_reg regs[$];
if (map_index.find(d)) begin
// Iterate over all registers in the map, set accesses
regs.delete();
maps[d].get_registers(regs);
// Registers with certain attributes are not to be tested
foreach (regs[i])
foreach (attribute_name[j]) begin
uvm_resource_db#(bit)::set({"REG::",regs[i].get_full_name()},attribute_name[j], 1);
end
end
endfunction