Hi, I am new to uvm. I am trying to build a uvm register backdoor access. I am trying something really simple before working on the actual design. Basically a single bit register “enable”. I got this error after compiled. I am sure I did something not right but I couldn’t figure it out. Any help would be appreciated. Thank you so much.
UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
BEFORE sample_reg.enable_i = null
** Fatal: (SIGSEGV) Bad handle or reference.
Time: 100 ns Iteration: 0 Process: /test_top/#INITIAL#23(#ublk#212496064#24) File: sample_reg_sequence.sv
Fatal error in Task design_sv_unit/sample_reg_sequence::run at sample_reg_sequence.sv line 24
HDL call sequence:
Stopped at sample_reg_sequence.sv 24 Task design_sv_unit/sample_reg_sequence::run - -
called from design.sv 34 - -
exit
End time: 18:07:15 on Jun 18,2020, Elapsed time: 0:00:06
Errors: 1, Warnings: 0
Done
/////////////////////
//sample_vreguvm.sv//
/////////////////////
import uvm_pkg::*;
`include “uvm_macros.svh”
class SAMPLE_REG_enable extends uvm_reg;
`uvm_object_utils(SAMPLE_REG_enable)
rand uvm_reg_field enable;
function new(string name = "SAMPLE_REG_enable");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
virtual function void build();
enable = uvm_reg_field::type_id::create("enable");
enable.configure(this, 1, 0, "RW", 0, 1'b0, 1, 1, 0);
add_hdl_path_slice(.name("enable"),.offset(0),.size(1));
endfunction
endclass
class SAMPLE_REG extends uvm_reg_block;
`uvm_object_utils(SAMPLE_REG)
rand SAMPLE_REG_enable enable_i;
uvm_reg_map SAMPLE_REG_map;
function new(string name = "SAMPLE_REG");
super.new(name, UVM_NO_COVERAGE);
endfunction
virtual function void build();
enable_i = SAMPLE_REG_enable::type_id::create("enable_i");
enable_i.configure(this);
enable_i.build();
SAMPLE_REG_map = create_map("SAMPLE_REG_map", 'h0, 4, UVM_LITTLE_ENDIAN, 1);
default_map = SAMPLE_REG_map;
SAMPLE_REG_map.add_reg(enable_i,'hc,"RW");
add_hdl_path(.path("sample"));
lock_model();
endfunction
endclass
//////////////////////////
//sample_reg_sequence.sv//
//////////////////////////
class sample_reg_sequence extends uvm_reg_sequence;
`uvm_object_utils(sample_reg_sequence)
SAMPLE_REG sample_reg;
function new (string name = “”);
super.new(name);
sample_reg = new;
endfunction
virtual task run();
uvm_status_e status;
//just trying to see if I can access enable_i
$display(“”);
$display(“BEFORE sample_reg.enable_i = %0d”, sample_reg.enable_i);
$display(“”);
#100; $cast(sample_reg,model);
//just trying to see if I can access enable_i
$display(“”);
$display(“AFTER sample_reg.enable_i = %0d”, sample_reg.enable_i);
$display(“”);
endtask
endclass
///////////////
//test_top.sv//
///////////////
include "sample_vreguvm.sv" include “sample_reg_sequence.sv”
`include “axi4_lite_master_interface.sv”
module test_top;
logic clk100M = 0, resetn_100M = 0;
initial forever #5 clk100M = ~clk100M;
initial
begin
resetn_100M = 0;
repeat (10) @(posedge clk100M); resetn_100M = 1;
end
axi4_lite_master_interface #(.ADDRESS_BUS_WIDTH(64),
.DATA_BUS_WIDTH (32 ))
axi4_lm_int(clk100M,resetn_100M);
initial
begin
sample_reg_sequence sample_reg_seq;
sample_reg_seq = new;
uvm_config_db#(virtual axi4_lite_master_interface
#(.ADDRESS_BUS_WIDTH(64),
.DATA_BUS_WIDTH (32 )))
::set(.cntxt(null),
.inst_name(“uvm_test_top*”),
.field_name(“axi4_lm_int”),
.value(axi4_lm_int));
sample_reg_seq.run;
end
endmodule
/////////////////////////////////
//axi4_lite_master_interface.sv//
/////////////////////////////////
interface axi4_lite_master_interface #(parameter ADDRESS_BUS_WIDTH=1,DATA_BUS_WIDTH=1)
(input bit s_axi_aclk, s_axi_aresetn);
logic [64-1:0] s_axi_awaddr = 0;
logic [2:0] s_axi_awprot;
logic s_axi_awvalid;
logic s_axi_awready;
logic [32-1:0] s_axi_wdata;
logic [3:0] s_axi_wstrb;
logic s_axi_wvalid;
logic s_axi_wready;
logic [1:0] s_axi_bresp;
logic s_axi_bvalid;
logic s_axi_bready;
logic [64-1:0] s_axi_araddr = 0;
logic s_axi_arvalid;
logic s_axi_arready;
logic [32-1:0] s_axi_rdata;
logic [1:0] s_axi_rresp;
logic [2:0] s_axi_arprot;
logic s_axi_rvalid;
logic s_axi_rready;
endinterface
/////////////
//sample.sv//
/////////////
module sample;
logic enable = 0;
endmodule