UVM REG ADAPTER

Hi,
can anyone tell me why this error is coming up and help to resolve it.?
please find the below code and error,

 class spi_reg_adapter extends uvm_reg_adapter;
 
 `uvm_object_utils(spi_reg_adapter)

  function new(string name = "spi_reg_adapter");
    super.new(name);
  endfunction
  
  virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
   
  //  spi_trans rt_spi_trans = spi_trans::type_id::create("rt_spi_trans");
  
 endfunction : reg2bus


  virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
 
   spi_trans rt_spi_trans;
   
    if (!$cast(rt_spi_trans, bus_item)) 
     begin
      assert($cast(rt_spi_trans,bus_item)) 
      else 
     `uvm_fatal (get_name()," SPI REG WR/RD to PCIe Register model - Failed bus item is not typecast with reg trans");
       return;
     end
   
    if(rt_spi_trans.pkt_type == WRITE)     
      begin  //{
        rw.kind  = UVM_WRITE;  
        rw.addr  = rt_spi_trans.address;
        rw.data  = rt_spi_trans.write_data;
      `uvm_info(get_type_name(),$sformatf(" TRANSACTION_TYPE : %h, ADDR : %h, DATA : %h ",rw.kind,rw.addr,rw.data),UVM_LOW)
      end //}
    else if(rt_spi_trans.pkt_type == READ)     
      begin  //{
        rw.kind  = UVM_WRITE;  
        rw.addr  = rt_spi_trans.address;
        rw.data  = rt_spi_trans.read_data;
      `uvm_info(get_type_name(),$sformatf(" TRANSACTION_TYPE : %h, ADDR : %h, DATA : %h ",rw.kind,rw.addr,rw.data),UVM_LOW)
      end //}

      rw.status = UVM_IS_OK;
 
  endfunction : bus2reg 

endclass : spi_reg_adapter

UVM_FATAL …/src/reg_model/spi_reg_adapter.svh(30) @ 27575.000ns: reporter [spi_adapter] SPI REG WR/RD to PCIe Register model - Failed bus item is not typecast with reg trans

Thanks,
Sandeep Gaur

In reply to Sandeep Gaur:

You cannot cast a uvm_reg_bus_op to your intended sequence item. You have to do what is essentially a copy. See Registers/Adapter | Verification Academy

In reply to dave_59:

Hi Dave,
I have done the same thing required in your example.
I am not casting the uvm_reg_bus_op to sequence_item. whereas I am casting bus_item to my sequence_item.

In reply to Sandeep Gaur:

Look like, you didn’t extend the “spi_trans” from uvm_sequence_item. you might have it extended from uvm_transaction.


class spi_trans extends uvm_sequence_item;

 //your transaction code

endclass : spi_trans 

you can also simplify code of type cast result checking.

if (!$cast(rt_spi_trans, bus_item)) 
begin
     //you don't need if and assert both for doing same thing. 
     //uvm_fatal stop the simulation. so no meaning of adding return after it. 
     `uvm_fatal (get_name()," SPI REG WR/RD to PCIe Register model - Failed bus item is not typecast with reg trans");
end

In reply to Rahulkumar Patel:

Hi Rahul,
I have extended my trans from uvm_sequence_item. but still the casting is not happening.

In reply to Sandeep Gaur:

did you connect the analysis port to the predictor?

   
//example code of connecting analysis port "reg_ana" to  analysis port of the predictor
 agt.reg_ana.connect(my_predict.bus_in);

did analysis port declared with transaction type spi_trans?


  uvm_analysis_port #(spi_trans) reg_ana;