UVM RAL. Model

I want to access register which had RW ,WO ,RO fields and I am doing random read followed by wrote So how to ignore the RO field in reg map when accessing all regsiters in writing and reading.,I don’t want to randomize the RO bits

In reply to dddvlsique:

To avoid to randomize the RO fields you should not declare them as rand in the RAL model.
RO fields will be ignored when writing a register with RO fields.