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  • UVM RAL sequences with priority

UVM RAL sequences with priority

UVM 6661
UVM RAL SEQUENCE 2 #RAL 11 sequence arbitration 4 sequencer arbitration 3
Po
Po
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12 posts
February 07, 2023 at 12:11 am

Hi,

Can anyone show me how to apply priority to UVM RAL sequences please? I have two RAL sequences, one does all the write operations and the other does all the read operations. Both sequences are started on the same sequencer. I'd like the write sequence to have higher priority than the read sequence while both sequences run at the same time. How can this be achieved?

I'm aware that with a non-RAL sequence, you can specify priority when calling the start() method, however, when I start my RAL sequences I pass in 'null' into the start() method argument. The sequencer is connected to the reg map in my uvm_environment.

I also tried using lock/unlock and grab/ungrab with RAL sequences, but these didn't work and were giving me the following error:

# UVM_FATAL (0) @101017ns [ GRAB] Null m_sequencer reference

Would anyone be able to point me to the right direction please? Any help is appreciated.

Kind regards,
Po

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chr_sue
chr_sue
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3846 posts
February 07, 2023 at 3:45 am

In reply to Po:

I think you do not need any priority for the sequences, Simply run the write and the read sequence in a series.

With respect to the grab probelm there is not enough information available. Could you put your exercise on EDAOlayground, please?

Po
Po
Full Access
12 posts
February 15, 2023 at 6:19 am

In reply to chr_sue:

Both read and write sequences need to run in parallel because I want to monitor the changes on the register values as the write operation happens.

With respect to the grab() problem, will you be able to advice how you use this in a RAL sequence please? The examples I find online are normally the standard UVM sequences which are initiated with the sequencer passed into the start() method. However, when I initiate the RAL sequence, I pass in 'null' into the start() method argument and the sequencer is connected to the reg map in my uvm_environment connect_phase() shown below.

register_model.reg_map.set_sequencer(sqr, register_model_adapter);
Po
Po
Full Access
12 posts
February 15, 2023 at 7:14 am

In reply to Po:

I just realised that grab/ungrab won't work in my case as there won't be any read while the sequencer is grabbed by the write sequence.

Is there a way to priorities a write operation over other read operation? For example, if a write operation is initiated it should be performed asap and while there's no write operations, the bus can be filled with read operations.

chr_sue
chr_sue
Full Access
3846 posts
February 15, 2023 at 7:21 am

In reply to Po:

You can execute a read directly after a write in a sequence. But this is a stupid way.
I'd recommend to execute all writes first, then randomize the register queue and start the read operations. This helps you to check if the writes are executed correctly.

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