Can anyone show me how to apply priority to UVM RAL sequences please? I have two RAL sequences, one does all the write operations and the other does all the read operations. Both sequences are started on the same sequencer. I’d like the write sequence to have higher priority than the read sequence while both sequences run at the same time. How can this be achieved?
I’m aware that with a non-RAL sequence, you can specify priority when calling the start() method, however, when I start my RAL sequences I pass in ‘null’ into the start() method argument. The sequencer is connected to the reg map in my uvm_environment.
I also tried using lock/unlock and grab/ungrab with RAL sequences, but these didn’t work and were giving me the following error:
Both read and write sequences need to run in parallel because I want to monitor the changes on the register values as the write operation happens.
With respect to the grab() problem, will you be able to advice how you use this in a RAL sequence please? The examples I find online are normally the standard UVM sequences which are initiated with the sequencer passed into the start() method. However, when I initiate the RAL sequence, I pass in ‘null’ into the start() method argument and the sequencer is connected to the reg map in my uvm_environment connect_phase() shown below.
I just realised that grab/ungrab won’t work in my case as there won’t be any read while the sequencer is grabbed by the write sequence.
Is there a way to priorities a write operation over other read operation? For example, if a write operation is initiated it should be performed asap and while there’s no write operations, the bus can be filled with read operations.
You can execute a read directly after a write in a sequence. But this is a stupid way.
I’d recommend to execute all writes first, then randomize the register queue and start the read operations. This helps you to check if the writes are executed correctly.