UVM RAL, how to model dependency from DUT pins

UVM
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1

Hi everybody,

I am pretty sure someone on this forum has already faced a similar issue and I am curious to listen to possible solutions.
Let’s say I have a nice UVM testbench environment with its own register model.
Some of the inputs of the DUT can have an effect on the value of certain registers, for example could make a field read-only rather than writable.

How can we model this behavior?
There are plenty of examples describing how to handle dependency from other registers but couldn’t find anything about DUT inputs.
I am really looking for a solution that would work both at block and system level.

Thanks in advance.

2

In reply to verif19:

Hi,

I’ve seen this kind of behaviours to be modelled using register_field callbacks post_predict this makes it reusable at block and system level

The following link has an example on how to use them, basically you can model most behaviours you need using them like ignoring writing to some fields, etc

HTH,

-R

3

In reply to rgarcia07:

Would you then pass the virtual interface handle inside the callback?

4

In reply to verif19:

I was thinking on having a component that monitors the DUT pins that modifies the registers fields behaviour, this component has a handle to the uvm reg model, then having your own class of register field extended from uvm_reg_field with a set of flags needed to model the desired behaviour, then using the callbacks to check the flags values for the specific fields when a write or read is applied to them.

Thus every time the DUT pins change, the component can update the register fields that are affected, not sure if it is the optimal solution but IMHO it can be reused at block and system level.

Using the virtual interface may work but what about if the pins change(in size etc) the component approach seems a little bit more adaptable.

HTH,

-Ronald