UVM RAL: How to implement common RAL accessed by two different addressing modes

UVM
,
1

Hi,

There are two different agents accessing common RAL but addressing is different for registers in memory.Each memory location is 32bits/4bytes wide as part of memory. Registers will be implemented as virtual registers. Below is sample.

ADDR1 ADDR2 Registers
0 0 REG_1
1 REG_2
3 REG_3
4 1 REG_4
5 REG_5
6 REG_6
7 REG_7

There will be two different reg_map for each of agent/interface. Agent 1 uses “ADDR1” and agent 2 uses “ADDR2” addressing schemes as above table. In explicit prediction of RAL, how two different reg maps can be used to access COMMON RAL. Each register will have different access policy for each of agents. Please suggest.

Any lead would be greatly appreciated. Thanks in advance.

2

In reply to rohithgm:

In the RAL you do not use the addresse to access the registers. You are using the register name. If you have 2 different maps they will reflect the different addressing. Also the access policies are contained in the specific map.

3

In reply to chr_sue:

Offset address have to be given for each of the registers while adding to reg_map. How this is handled without giving address and only with register name?