UVM question

I am doing AHB to APB bridge, in the scoreboard, I compare HWDATA and PWDATA but I have data in ahb driver class run phase which does not stop executing of result
i have following ahb trans file

`ifndef AHB_TRANS
`define AHB_TRANS
import ahb_enum_pkg::*; // we are using import because type definitions are scope specific.
class ahb_trans extends uvm_sequence_item;

	rand bit HREADYin ;
	rand     rstn_enum HRESETn;

	//AHB Control Signals
	rand txn_enum       HTRANS;	    // Indica tes the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE or BUSY.
	rand hsize_enum     HSIZE;	    // Indicates the size of the transfer,(byte,halfword,word) max 1024bit.
	rand burst_enum     HBURST;   	// Indicates if the transfer forms part of a burst.(4,8,16).
	rand write_enum     HWRITE;	    // When HWRITE is HIGH, this signal indicates a write transfer and the master will broadcast data on the write data bus	
	     
		 bit   [31:0] AHB_EXP_DATA;
	     logic [31:0] HRDATA;
	rand bit   [31:0] STARTING_HADDR;	// 32-bit system HADDR_Q bus.
	rand bit   [31:0] HWDATA;	        // write data bus is used to transfer data from the master to the bus slaves during write operations.
    rand bit   [ 3:0] HSELx;          //Slave select signal indicates that the current transfer is intended for the selected signal.
    	
	//AHB Outputs	
	     bit [1:0]HRESP; //Output
	rand bit      HREADYout;
	
	//port declare
		 bit [31:0] lower_wrap_boundary;
		 bit [31:0] upper_wrap_boundary;   
		 bit [31:0] aligned_addr;
	rand 			bl_enum BLENTH;
		 int 		NEXT_HADDR;
	
    // for array declare 
    rand int unsigned hwdata_q[$];
         int unsigned haddr_q [$] ;
	
	constraint size_limit{	HSIZE inside {bytes, halfword, word};}
	
	//constraint trans_type {HTRANS != BUSY;}
	
    //HBURST
    constraint BURST { HBURST inside {[0:7]};}  
    constraint EXP1  {hwdata_q.size() == BLENTH;}				 
	constraint EXP2  {foreach(hwdata_q[i]) hwdata_q[i] < 2000;}
	constraint EXP3  {     if (HBURST inside {SINGLE})       {BLENTH == BL_ONE;}
	                  else if (HBURST inside {INCR})         {BLENTH == BL_TWO;}
	                  else if (HBURST inside {WRAP4,INCR4})  {BLENTH == BL_FOUR;}
	                  else if (HBURST inside {WRAP8,INCR8})  {BLENTH == BL_EIGHT;}
	 		          else if (HBURST inside {WRAP16,INCR16}){BLENTH == BL_SIXTEEN;}}
	constraint EXP4 {STARTING_HADDR < 1000;} 
	
    // Register with Factory
	`uvm_object_utils_begin(ahb_trans)
		`uvm_field_enum(rstn_enum,HRESETn, UVM_ALL_ON)
		`uvm_field_int (HREADYin,          UVM_ALL_ON)
		`uvm_field_enum(txn_enum,HTRANS,   UVM_ALL_ON)
		`uvm_field_enum(burst_enum,HBURST, UVM_ALL_ON)
		`uvm_field_enum(hsize_enum,HSIZE,  UVM_ALL_ON)
		`uvm_field_enum(write_enum,HWRITE, UVM_ALL_ON) 
		`uvm_field_int (STARTING_HADDR,    UVM_ALL_ON)
		`uvm_field_int (HWDATA,            UVM_ALL_ON)
		`uvm_field_int (HRDATA,            UVM_ALL_ON)
		`uvm_field_int (HRESP,	           UVM_ALL_ON)
		`uvm_field_int (HREADYout,         UVM_ALL_ON)
	`uvm_object_utils_end
    
							
	//------------------------------------------------------------------------------------------------------
	// method name : new(Constructor)
	// argu : string name and handle of uvm_component.
	// discription : Instead of new method use create method to create component in uvm hierarchy.
	//-------------------------------------------------------------------------------------------------------
	function new(string name = "ahb_trans");
		super.new(name);
	endfunction:new
	
	//------------------------------------------------------------------------------------------------------
	// BURST LOGIC IMPLEMENTATION
	//-------------------------------------------------------------------------------------------------------	
	function void post_randomize();
	
	//-------------------------------------------------------------------------------------------------------
	// BURST CALCULATION FOR WRITE ADDR
	//-------------------------------------------------------------------------------------------------------		
		haddr_q = {};
		aligned_addr = (STARTING_HADDR - (STARTING_HADDR %(2**HSIZE)));
		
	//--------------------------------------------------------------------------------------------------------
	// WRAP BURST LOGIC
	//-------------------------------------------------------------------------------------------------------- 	
		lower_wrap_boundary = (STARTING_HADDR/((2**HSIZE)*BLENTH))*((2**HSIZE)*BLENTH);
		upper_wrap_boundary = ( lower_wrap_boundary + ((2**HSIZE)*BLENTH));
		$display("aligned_addr = %0d, lower_wrap_boundary = %0d, upper_wrap_boundary = %0d",aligned_addr,lower_wrap_boundary,upper_wrap_boundary);		
		NEXT_HADDR = STARTING_HADDR;
		repeat(BLENTH)begin
		
	//---------------------------------------------------------------------------------------------------------
	// FIXED & INCR BURST LOGIC
	//----------------------------------------------------------------------------------------------------------
			 haddr_q.push_back(NEXT_HADDR);
			 NEXT_HADDR = NEXT_HADDR + (2**HSIZE);
			 
			 if(( HBURST == WRAP4 || HBURST == WRAP8 || HBURST == WRAP16) && NEXT_HADDR == upper_wrap_boundary)
			 NEXT_HADDR = lower_wrap_boundary;

		 end
		 	$display("STARTING_HADDR = %d, HSIZE = %d, HBURST = %d, BLENTH = %d",STARTING_HADDR,HSIZE,HBURST,BLENTH);
		 	$display("STARTING_HADDR = %p",haddr_q);
			$display("hwdata_q = %p",hwdata_q);	
			$display("--------------------------------------------------------------------------------------------------------------------------------------------");
	endfunction
	
endclass:ahb_trans
`endif

and the ahb driver as following

`ifndef AHB_DRIVER
`define AHB_DRIVER
import ahb_enum_pkg::*; // we are using import because type definitions are scope specific.

class ahb_driver extends uvm_driver#(ahb_trans);

	//Factory Registration
	`uvm_component_utils(ahb_driver)
	
	//Virtual Interface Handle
	virtual main_interface.HDR_MP vif;

	//AHB Transaction Handle
	ahb_trans ahb_txn;
		
	//--------------------------------------------------------------------------------------------
	// method name : new(Constructor)
	// argu : string name and handle of uvm_component.
	// discription : Instead of new method use create method to create component in uvm hierarchy.
	//--------------------------------------------------------------------------------------------
	function new(string name = "ahb_driver", uvm_component parent);
		super.new(name, parent);
	endfunction
	
	//--------------------------------------------------------------------------------------------
	// method name : start
	// discription : 
	//--------------------------------------------------------------------------------------------	
    task start();
		@(vif.ahb_drv_cb);
  		vif.ahb_drv_cb.HRESETn <= reset;
		@(vif.ahb_drv_cb);
		vif.ahb_drv_cb.HRESETn <= set;
 	endtask
	
	//--------------------------------------------------------------------------------------------
	// method name : run_phase
	// argu : phase
	// discription : Generate stimulus
	//--------------------------------------------------------------------------------------------
	task run_phase(uvm_phase phase);
	   ahb_txn = ahb_trans::type_id::create("ahb_txn",this);
   // `uvm_info("ahb_driver","in run phase before forever",UVM_LOW)

	  start();
		forever
		begin
			`uvm_info("ahb_driver","in run phase after forever",UVM_LOW)
			seq_item_port.get_next_item(req);
			`uvm_info("ahb_driver"," get_next_item",UVM_LOW)
			send_to_dut(req);
			seq_item_port.item_done();
			`uvm_info("ahb_driver"," item done",UVM_LOW)
		end
		    //`uvm_info("ahb_driver","in run phase after end task",UVM_LOW)


	endtask //run_phase

	//--------------------------------------------------------------------------------------------
	// method name : send_to_dut
	// argu : req
	// discription : 
	//--------------------------------------------------------------------------------------------
	task send_to_dut(ahb_trans req);
	//reset 
		 @(vif.ahb_drv_cb);
   		 vif.ahb_drv_cb.HWRITE <= req.HWRITE;
		 $display("HWRITE %d", req.HWRITE);
		 vif.ahb_drv_cb.HBURST <= req.HBURST;
		 vif.ahb_drv_cb.HREADYin <= req.HREADYin;
  		 //  vif.ahb_drv_cb.HREADYout <= req.HREADYout;
		 vif.ahb_drv_cb.HTRANS <= NONSEQ;
		 vif.ahb_drv_cb.HSIZE <= req.HSIZE;
         vif.ahb_drv_cb.STARTING_HADDR <= req.haddr_q.pop_front();
    
		foreach(req.BLENTH)
		//repeat(9)
			begin
				@(vif.ahb_drv_cb iff vif.ahb_drv_cb.HREADYout==1);
				if(req.haddr_q.size()!=0)begin
				vif.ahb_drv_cb.STARTING_HADDR <= req.haddr_q.pop_front();
				//$display("starting addr = %d",vif.ahb_drv_cb.STARTING_HADDR);
				end			
				vif.ahb_drv_cb.HTRANS <= SEQ;
				if(req.HWRITE && req.hwdata_q.size() !== 0)begin
				//vif.ahb_drv_cb.HWDATA <= req.hwdata_q[i];
				vif.ahb_drv_cb.HWDATA <= req.hwdata_q.pop_front();
				end
				//$strobe("hwdata = %d,time = %t",vif.ahb_drv_cb.HWDATA,$time);
				wait(vif.ahb_drv_cb.HREADYout);
			end
				//$display("blanth === %d",req.BLENTH );			

				//vif.ahb_drv_cb.HRESETn <= reset;
    endtask


endclass: ahb_driver
`endif

and I have following output of command prompt

# aligned_addr = 752, lower_wrap_boundary = 736, upper_wrap_boundary = 768
# STARTING_HADDR =        755, HSIZE = 2, HBURST = 4, BLENTH =  8
# STARTING_HADDR = '{755, 759, 763, 767, 771, 775, 779, 783}
# hwdata_q = '{209, 514, 266, 455, 100, 739, 592, 329}
# --------------------------------------------------------------------------------------------------------------------------------------------
# UVM_INFO ../ahb/ahb_driver.sv(59) @ 15: uvm_test_top.env_h.ahb_hagent_h.ahb_drv [ahb_driver]  get_next_item
# HWRITE 1
# UVM_INFO ../ahb/ahb_driver.sv(62) @ 195: uvm_test_top.env_h.ahb_hagent_h.ahb_drv [ahb_driver]  item done
# UVM_INFO ../ahb/ahb_driver.sv(57) @ 195: uvm_test_top.env_h.ahb_hagent_h.ahb_drv [ahb_driver] in run phase after forever

while I display scoreboard data it never exit from run phase

In reply to kartik@23Patel:

Is your question that the simulation does not stop? Or what is your question.
You do not show where you have your objections implemented and you do not show the sequences you are running.

are you dropping the objection in test class? also, where is your sequence class? Did you check the DUT is driving HREADYout?