UVM @(posedge interface.clock) hangs

UVM
1

I have a UVM testbench, with 2 instances of following uvm_component:

class my_driver ...
  virtual interface my_vif;
  task my_task
    ...
    @(posedge my_vif.clk);
    my_vif.a = 1;
    ...
  endtask
endclass

Virtual interface is tied to 2 different physical modules in design for these 2 driver instances.

The problem is that logic before @posedge for both instances gets called. However, only one instance goes through @posedge, and moves to my_vif.a =1 statement, while the other stucks at posedge, so never moves to next statement. Does anybody know the reason?

Thank you!

2

In reply to josephazh:

Is this correct? One interface is connected to 2 agents, i.e. they are dependent on each other?

3

In reply to chr_sue:

It is virtual interface. At top level, each virtual interface has been tied to a physical interface.

4

In reply to josephazh:

Without seeing more code it is ipossible to give an advise.

5

In reply to josephazh:

You may check - is the stucked driver’s virtual interface connected correctly? If yes, is the physical interface’s clock running?