UVM Phases are virtual or non vritual

UVM
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1

Hi,
I have seen some places’ build phase is declared as virtual and some places non-virtual. what’s the difference between both of them and which one is recommended in what scenario?
ex:

function void build_phase(uvm_phase phase);

virtual function void build_phase(uvm_phase phase);

why in the build phase it is important to call super.build_phase.

Thanks.

2

In reply to Abuzar Gaffari:

In SystemVerilog, once a method gets declared as
virtual in a base class, it remains virtual in all derived classes. The
virtual keyword becomes optional. I suggest always being explicit and using it.

If you use the `uvm_field_* automation macros in a uvm_component, some functionality will not work unless you call super.build_phase(). We recommend against using the field automation macros.