UVM Overriding : is it possible to revert existing overriding?

UVM
,
1

Hi All,

I have very strange requirement, where i have following base class.


class base_monitor extends uvm_monitor;
   ...
   
   virtual function xyz_operation();
    // Logic 1 is performed
   endfunction : xyz_operation
   ...
endclass

Now, due to certain extra requirement i have to override base_monitor with following extended_monitor.

class extended_monitor extends base_monitor;
   ...
   
   virtual function xyz_operation();
    // Logic 2 is performed
   endfunction : xyz_operation
   ...
endclass

Now, for verification of most of scenarios, i have to use xyz_operation() method of extended_monitor, as base_monitor doesn’t have such support and i can not remove base_monitor from hierarchy. so, i performed overriding of base_monitor with extended_monitor.
But for verification of some additional features, i have to use xyz_operation() method of extended_monitor initially, then have to use xyz_operation() method of base for some time(Corruption of data path), and then back to xyz_operation() method of extended at the end in single seed simulation. as extended_monitor doesn’t have support for such feature. and i don’t want to change any code in extended_monitor or base_monitor.
So, question is simple, Does uvm provides any support to remove/add overriding of components run time? can anyone please suggest the appropriate scenario to overcome this?

Thanks and Regards,
Mitesh Patel

2

In reply to mitesh.patel:

SystemVerilog does not allow you to dynamically control how overrides work once an object has been constructed. But you can create the effect of dynamic control by structuring your code like

class extended_monitor extends base_monitor;
   ...
   virtual function void xyz_operation();
      if (some_condition)
          super.xyz_operation() // Logic 2 is performed
      else begin
    // Logic 2 is performed
      end
   endfunction : xyz_operation
   ...
endclass