UVM objection use

I have a design with an IP that goes through a calibration process after reset. I pulse the reset through my driver in a sequence item and end the body task. In the monitor, I am waiting for the calibration done bit to be set, I am calling the wait task in the monitor run phase. I see that the simulation ends after the sequence item body task is done. The simulation ends without waiting for the monitor wait task to finish.

Is raising an objection in the monitor run phase and dropping it after the wait task is done, a valid way to solve this? Do you have any recommendations on how/if I can improve my testbench structure?

In reply to rthakur1:

I approach these situations in a similar manner that the software team would:

  • Is there a register that indicates that the calibration is done? If so, create a sequence that reads this register until the bit is set.
  • Is there an interrupt signal? If so, create a sequence that waits until the interrupt is generated.

In any case, there should be a sequence that doesn’t complete until the calibration process is complete.

In reply to cgales:

That makes sense. I guess I chose to poll for it in the monitor class because I was “monitoring” for calibration done. Thank you for your help!