Hi All,
I am new to FSM based verification environments.
In DUT(memory controller) ,we are having FSM.I am going to implement monitor in uvm.
DUT don’t have any signal to represent current state of state machine.
Now ,i am in dilemma,how to collect the info form dut for each state.
or for state machine based duts,is there any other ways to implement monitor(what kind of checks to be done here??) checks?.
Please let me know.
Thanks & Regards,
Nagendra.
In reply to gani:
Hi Nagendra,
There is a very less probability of having any signal on the bus representing the FSM state.
One of the possible ways to verify the FSM transition is to write checkers/assertions for them.
Following the post for some better approach.
Regards,
Aswin.
In reply to Aswin_VA:
While you may not have signals on the bus to represent the FSM state, I’m sure there’s a bit-vector somewhere that does. You could create a separate SV interface with a set of signals bound to the FSM vector. Then, you could treat this just like any other interface and write a monitor for it. The monitor could sense when the state changes and report that as a transaction via its analysis port. The real question to ask yourself is what you want to do with the information. If it will be used to control some other aspect of the testbench, or even to be recorded in a covergroup, then this interface-monitor approach would be fine. If all you want to do is to make sure that you don’t take any illegal transitions, then using assertions is probably the best way. Then you can use formal to guarantee the correctness of your FSM and you don’t need to worry about it in your UVM testbench.
In reply to tfitz:
Hi ,
i have a Memory controller(MC) ,it will drive Memory model(MM)
MC------------->MM
here in MC ,i am sending particular command to driver.i have an enum type to represent state.so i know what will the next cmd ,in test case one by one command passing to MC driver.
Now MM should act like a rtl.it should collect the info from MM interface(integrating Mc intf TO MM intf in top).
Model has to check all timing issues & need to store data in memory(if it is write based on particular bank info).if it is a read need to read from memory.
1)Interface don’t have any signal to represent current state of state machine.
i have CA(data,cmd,ba…multiplexed)
2)Initially i will send config reg setting through MC to MM.Can i collect this info using ral model in MM?
3)i think ,need to implement MM as a slave should collect all the info from MC & responds to timings & need to do seq recreation & send it back.
Please give me ,over view of verification environment for FSM based slave models.
requesting for any link & white papers,which is useful .
Thanks,
Nagendra.