Uvm to module error

Hi,
I have posted the same issue, on some suggestion i have modified it but still facing the same issue. I have attached my code link.
uvm_adder(1) - EDA Playground.

error message
Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 3: token is ‘module’
module top;
^

In reply to dkumar264:

When you get a syntax error on what looks like a perfectly fine piece of code, you need to look backwards at the code before it. Usually a missing ‘;’ or end-something.

In reply to dave_59:

In reply to dkumar264:
When you get a syntax error on what looks like a perfectly fine piece of code, you need to look backwards at the code before it. Usually a missing ‘;’ or end-something.

hi dave
when i comment some test lines there is no error & i have checked all my classes it looks fine for me, dono where the error is.

In reply to dkumar264:

I see a missing endclass. There are many other errors once you fix that.

You are going to need a better debugging process. Perhaps write and compile one class at a time. Only go on to the next class after the previous class compiles cleanly.

In reply to dkumar264:

You asked the same question yesterday in another thread and I was recommending to run your code with another Simulator.
I had a short look to your code and saw many Things which are not correct, very stupid things like typos/case sensitivity etc.
Se here the whole list Aldec is issuing:

ERROR VCP2000 “Syntax error. Unexpected token: uvm_sequence_item[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “seq_item.sv” 1 41
ERROR VCP2000 “Syntax error. Unexpected token: rand[_RAND]. The ‘rand’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “seq_item.sv” 3 7
ERROR VCP5018 “Macro uvm_object_utils_begin is not defined.” “seq_item.sv” 5 26
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “seq_item.sv” 5 27
ERROR VCP5018 “Macro uvm_field_int is not defined.” “seq_item.sv” 6 17
ERROR VCP5018 “Macro uvm_field_int is not defined.” “seq_item.sv” 7 17
ERROR VCP5018 “Macro uvm_field_int is not defined.” “seq_item.sv” 8 17
ERROR VCP5018 “Macro uvm_field_int is not defined.” “seq_item.sv” 9 17
ERROR VCP5018 “Macro uvm_object_utils_end is not defined.” “seq_item.sv” 10 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “seq_item.sv” 11 15
ERROR VCP2000 “Syntax error. Unexpected token: ). Expected tokens: ‘,’ , ‘;’.” “seq_item.sv” 11 39
ERROR VCP2000 “Syntax error. Unexpected token: uvm_sequence[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “sequence.sv” 1 33
ERROR VCP5018 “Macro uvm_object_utils is not defined.” “sequence.sv” 2 20
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “sequence.sv” 4 15
ERROR VCP2000 “Syntax error. Unexpected token: ). Expected tokens: ‘,’ , ‘;’.” “sequence.sv” 4 39
ERROR VCP5237 “Undefined class: type_id.” “sequence.sv” 10 34
ERROR VCP2000 “Syntax error. Unexpected token: endclass[_ENDCLASS]. The ‘endclass’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “sequence.sv” 16 13
ERROR VCP2000 “Syntax error. Unexpected token: uvm_sequencer[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “sequencer.sv” 1 35
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “sequencer.sv” 2 23
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “sequencer.sv” 4 15
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “sequencer.sv” 4 48
ERROR VCP2000 “Syntax error. Unexpected token: uvm_driver[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “driver.sv” 1 29
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “driver.sv” 3 23
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “driver.sv” 3 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “driver.sv” 5 15
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “driver.sv” 5 48
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “driver.sv” 9 44
ERROR VCP5018 “Macro uvm_fatal is not defined.” “driver.sv” 12 15
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “driver.sv” 15 41
ERROR VCP2000 “Syntax error. Unexpected token: uvm_monitor[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “monitor.sv” 1 30
ERROR VCP2000 “Syntax error. Unexpected token: uvm_analysis_port[_IDENTIFIER]. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “monitor.sv” 3 20
ERROR VCP2505 “Duplicate identifier: name” “monitor.sv” 4 15
ERROR VCP2505 “Duplicate identifier: name” “monitor.sv” 4 15
ERROR VCP2505 “Duplicate identifier: name” “monitor.sv” 4 15
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “monitor.sv” 5 23
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “monitor.sv” 5 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “monitor.sv” 7 15
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “monitor.sv” 7 58
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “monitor.sv” 13 44
ERROR VCP5018 “Macro uvm_fatal is not defined.” “monitor.sv” 16 15
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “monitor.sv” 19 41
ERROR VCP2000 “Syntax error. Unexpected token: uvm_agent[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “agent.sv” 6 28
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “agent.sv” 10 23
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “agent.sv” 10 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “agent.sv” 12 15
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “agent.sv” 12 54
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “agent.sv” 16 44
ERROR VCP5237 “Undefined class: type_id.” “agent.sv” 20 34
ERROR VCP5237 “Undefined class: type_id.” “agent.sv” 21 31
ERROR VCP5237 “Undefined class: type_id.” “agent.sv” 23 27
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “agent.sv” 26 46
ERROR VCP2000 “Syntax error. Unexpected token: uvm_scoreboard[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “scoreboard.sv” 1 33
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “scoreboard.sv” 6 23
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “scoreboard.sv” 6 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “scoreboard.sv” 8 15
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “scoreboard.sv” 8 61
ERROR VCP2000 “Syntax error. Unexpected token: task[_TASK]. Expected tokens: ‘(*’ , ‘interface’ , ‘full_case’ , ‘parallel_case’ , ‘parallel_case full_case’ … .” “scoreboard.sv” 18 15
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “scoreboard.sv” 18 41
ERROR VCP2000 “Syntax error. Unexpected token: uvm_env[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “enviornment.sv” 3 26
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “enviornment.sv” 4 23
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “enviornment.sv” 8 15
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’.” “enviornment.sv” 8 16
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “enviornment.sv” 8 54
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “enviornment.sv” 12 44
ERROR VCP5237 “Undefined class: type_id.” “enviornment.sv” 14 28
ERROR VCP5237 “Undefined class: type_id.” “enviornment.sv” 15 28
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “enviornment.sv” 18 46
ERROR VCP2000 “Syntax error. Unexpected token: uvm_test[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “test.sv” 2 28
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “test.sv” 3 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “test.sv” 8 15
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’.” “test.sv” 8 16
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “test.sv” 8 48
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “test.sv” 12 44
ERROR VCP5237 “Undefined class: type_id.” “test.sv” 14 27
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “test.sv” 18 41

In reply to dave_59:

thank u

In reply to chr_sue:

In reply to dkumar264:
You asked the same question yesterday in another thread and I was recommending to run your code with another Simulator.
I had a short look to your code and saw many Things which are not correct, very stupid things like typos/case sensitivity etc.
Se here the whole list Aldec is issuing:
ERROR VCP2000 “Syntax error. Unexpected token: uvm_sequence_item[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “seq_item.sv” 1 41
ERROR VCP2000 “Syntax error. Unexpected token: rand[_RAND]. The ‘rand’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “seq_item.sv” 3 7
ERROR VCP5018 “Macro uvm_object_utils_begin is not defined.” “seq_item.sv” 5 26
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “seq_item.sv” 5 27
ERROR VCP5018 “Macro uvm_field_int is not defined.” “seq_item.sv” 6 17
ERROR VCP5018 “Macro uvm_field_int is not defined.” “seq_item.sv” 7 17
ERROR VCP5018 “Macro uvm_field_int is not defined.” “seq_item.sv” 8 17
ERROR VCP5018 “Macro uvm_field_int is not defined.” “seq_item.sv” 9 17
ERROR VCP5018 “Macro uvm_object_utils_end is not defined.” “seq_item.sv” 10 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “seq_item.sv” 11 15
ERROR VCP2000 “Syntax error. Unexpected token: ). Expected tokens: ‘,’ , ‘;’.” “seq_item.sv” 11 39
ERROR VCP2000 “Syntax error. Unexpected token: uvm_sequence[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “sequence.sv” 1 33
ERROR VCP5018 “Macro uvm_object_utils is not defined.” “sequence.sv” 2 20
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “sequence.sv” 4 15
ERROR VCP2000 “Syntax error. Unexpected token: ). Expected tokens: ‘,’ , ‘;’.” “sequence.sv” 4 39
ERROR VCP5237 “Undefined class: type_id.” “sequence.sv” 10 34
ERROR VCP2000 “Syntax error. Unexpected token: endclass[_ENDCLASS]. The ‘endclass’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “sequence.sv” 16 13
ERROR VCP2000 “Syntax error. Unexpected token: uvm_sequencer[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “sequencer.sv” 1 35
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “sequencer.sv” 2 23
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “sequencer.sv” 4 15
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “sequencer.sv” 4 48
ERROR VCP2000 “Syntax error. Unexpected token: uvm_driver[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “driver.sv” 1 29
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “driver.sv” 3 23
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “driver.sv” 3 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “driver.sv” 5 15
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “driver.sv” 5 48
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “driver.sv” 9 44
ERROR VCP5018 “Macro uvm_fatal is not defined.” “driver.sv” 12 15
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “driver.sv” 15 41
ERROR VCP2000 “Syntax error. Unexpected token: uvm_monitor[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “monitor.sv” 1 30
ERROR VCP2000 “Syntax error. Unexpected token: uvm_analysis_port[_IDENTIFIER]. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “monitor.sv” 3 20
ERROR VCP2505 “Duplicate identifier: name” “monitor.sv” 4 15
ERROR VCP2505 “Duplicate identifier: name” “monitor.sv” 4 15
ERROR VCP2505 “Duplicate identifier: name” “monitor.sv” 4 15
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “monitor.sv” 5 23
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “monitor.sv” 5 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “monitor.sv” 7 15
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “monitor.sv” 7 58
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “monitor.sv” 13 44
ERROR VCP5018 “Macro uvm_fatal is not defined.” “monitor.sv” 16 15
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “monitor.sv” 19 41
ERROR VCP2000 “Syntax error. Unexpected token: uvm_agent[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “agent.sv” 6 28
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “agent.sv” 10 23
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “agent.sv” 10 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “agent.sv” 12 15
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “agent.sv” 12 54
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “agent.sv” 16 44
ERROR VCP5237 “Undefined class: type_id.” “agent.sv” 20 34
ERROR VCP5237 “Undefined class: type_id.” “agent.sv” 21 31
ERROR VCP5237 “Undefined class: type_id.” “agent.sv” 23 27
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “agent.sv” 26 46
ERROR VCP2000 “Syntax error. Unexpected token: uvm_scoreboard[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “scoreboard.sv” 1 33
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “scoreboard.sv” 6 23
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’ , ‘checker’ , ‘function’ , ‘task’ , ‘timeprecision’ … .” “scoreboard.sv” 6 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “scoreboard.sv” 8 15
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “scoreboard.sv” 8 61
ERROR VCP2000 “Syntax error. Unexpected token: task[_TASK]. Expected tokens: ‘(*’ , ‘interface’ , ‘full_case’ , ‘parallel_case’ , ‘parallel_case full_case’ … .” “scoreboard.sv” 18 15
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “scoreboard.sv” 18 41
ERROR VCP2000 “Syntax error. Unexpected token: uvm_env[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “enviornment.sv” 3 26
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “enviornment.sv” 4 23
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “enviornment.sv” 8 15
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’.” “enviornment.sv” 8 16
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “enviornment.sv” 8 54
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “enviornment.sv” 12 44
ERROR VCP5237 “Undefined class: type_id.” “enviornment.sv” 14 28
ERROR VCP5237 “Undefined class: type_id.” “enviornment.sv” 15 28
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “enviornment.sv” 18 46
ERROR VCP2000 “Syntax error. Unexpected token: uvm_test[_IDENTIFIER]. Expected tokens: ‘$unit’ , ‘user-defined type’ , ‘class as type’.” “test.sv” 2 28
ERROR VCP5018 “Macro uvm_component_utils is not defined.” “test.sv” 3 24
ERROR VCP2000 “Syntax error. Unexpected token: new[__NEW]. The ‘new’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “test.sv” 8 15
ERROR VCP2000 “Syntax error. Unexpected token: (. Expected tokens: ‘;’.” “test.sv” 8 16
ERROR VCP2000 “Syntax error. Unexpected token: parent[_IDENTIFIER]. Expected tokens: ‘=’ , ‘[’ , ‘,’ , ‘;’.” “test.sv” 8 48
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “test.sv” 12 44
ERROR VCP5237 “Undefined class: type_id.” “test.sv” 14 27
ERROR VCP2000 “Syntax error. Unexpected token: phase[_IDENTIFIER]. Expected tokens: ‘[’ , ‘)’ , ‘,’ , ‘=’.” “test.sv” 18 41

hi,
even i got the same error when i changed simulator to aldec. i got the output in vcs but aldec shows some error i dono y.

In reply to dkumar264:

You havent wrote
import uvm_pkg::*;
`include “uvm_macros.svh”

mention in your top module

as

import uvm_pkg::*;
include "uvm_macros.svh" include “interface.sv”
`include “test.sv”
module top;
in i();

half tb(.a(i.a),.b(i.b),.sum(i.sum),.carry(i.carry));
initial begin

  uvm_config_db#(virtual in)::set(null,"*","in",i);



  run_test("test");

end
endmodule