Uvm messages in property

UVM
1 
//with `UVM_ERROR Macro - 1ST CODE
`ifndef DDR2_MSG_ERR
       `define DDR2_MSG_ERR(id,msg) `uvm_error(id,msg)
  `endif

property p_ddr2_nop_aftr_precharge_all(assert_id,msg);
       @(posedge ddr2_intf.clk) (`PRECHARGE_ALL_OP) |->  ##[0:20000000] ((!`NOP_OP),`DDR2_MSG_ERR(assert_id,msg));
 endproperty : p_ddr2_nop_aftr_precharge_all

assert property(p_ddr2_nop_aftr_precharge_all("PRECHARGE_CHECK","FAILED"))

else begin
  $display("Passed");
end

//With $error - 2ND CODE

property p_ddr2_nop_aftr_precharge_all(assert_id,msg);
       @(posedge ddr2_intf.clk) (`PRECHARGE_ALL_OP) |->  ##[0:20000000] ((!`NOP_OP),$error("FAILED ::%s",{assert_id,msg}));
 endproperty : p_ddr2_nop_aftr_precharge_all

assert property(p_ddr2_nop_aftr_precharge_all("PRECHARGE_CHECK","FAILED"))

else begin
  $display("Passed");
end

1st Code : I have used UVM_ERROR, Simulator is not taking and we are getting Compile error.
2nd COde : I have used $error, Now its working fine.

Can someone tell me Why this is happening? If I want to use uvm display messages , What is the solution?

2

In reply to janudeep3:

Please re-check your your posted example. They do not use UVM_ERROR or $error. And show us your compiler error.

3

#1 style - compile error is likely due to begin/end expansion of uvm_error macro. If you really need that error as "sequence match item" (as you have coded, wrap this in a function and do it. But I believe your fail-action-block should invoke the uvm_error, why do you say “Passed” over there? Kind of strange usage.

Srini
http://www.verifworks.com

4

In reply to Srini @ CVCblr.com:

Thanks Srini. By wrapping it in a function, we got it. That passed message is just a display to debug, its not the exact code