what are some of the limitations of UVM. I want to ask this as I got familiar with E-UVM which is called Embedded-UVM which says UVM cannot be used to make multicore testbenches and therefore not used to make H/W tests which are used in emulation.
2)If we get to compare both what will you say are the advantages and disadvantages of both?.
3)If We consider UVM for emulation what are the basic Hardware/software requirements necessary (I.e whether EDA's simulator is multicore enabled , How Testbench is layered over when run multithread (single but shared RAM etc).
4) I have trouble understanding role of H/w specific Tests over FPGA's .Does this means ,Once
we dump our DUT-HDL design on the FPGA . its performance is monitored by different UVM- tests and just like the design we can also dump testcases on it ? (I want a basic knowledge to get started with UVM in emulation )
