UVM- issue with nested sequence with get config_db

UVM
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1 
I'm trying to run a sequence (seq_write) for certain number of times from another sequence (seq_wr_rand) using `uvm_do. The base sequence has a variable updated through get config_db. 
The problem is, seq_wr_rand is getting the proper config_db value, whereas the sequence being called (seq_write) from it is not getting the config_db value and my test fails. I'm expecting write with value x61, whereas the actual is x14. The code & output snippets are below.

Similar to this, i've many like this. Can someone plz tell what things i'm doing wrong to get output like this???

CODE:


class base_sequence extends uvm_sequence #(data_item);
  bit [9:0] addr_cfgd=20;
  dev_config  cfg;
  `uvm_object_utils(base_sequence)
  function new(string name="base_sequence");
    super.new(name);
  endfunction
  virtual task pre_body();
      super.pre_body();
      if (starting_phase!=null) begin
         starting_phase.raise_objection(this);
      end
     if(!uvm_config_db #(dev_config)::get(null, get_full_name(), "dev_config", cfg))  
          `uvm_fatal(get_type_name(), "dev_config config_db lookup failed")
     addr_cfgd=cfg.addr_cfgdve_address;
    `uvm_info(get_type_name(),  $sformatf("addr_cfgd = x%0h",addr_cfgd), UVM_FULL )
  endtask
endclass : base_sequence

class seq_write extends base_sequence;
   `uvm_object_utils(seq_write)
   function new(string name = "seq_write");
     super.new(name);
   endfunction
   task body();
     data_item req;
     begin
      `uvm_info(get_type_name(), $sformatf("Executing WRITE @ x%h",addr_cfgd), UVM_LOW)
       req = data_item::type_id::create("req");
       start_item(req);
       assert(req.randomize() with {reqst == WRITE;address == addr_cfgd;});
       `uvm_info(get_type_name(),$sformatf("%s reqst %s: addr = `x%0h, data.size = `x%0h",get_sequence_path(), req.reqst,req.address, req.data.size()),UVM_FULL);
       finish_item(req);
     end
   endtask
endclass:seq_write

class seq_wr_rand extends base_sequence;
  rand shortint [5:0] count;
 `uvm_object_utils(seq_wr_rand)
  constraint limit {count > 0; count < 10;}
  
 function new(string name = "seq_wr_rand");
    super.new(name);
 endfunction
  virtual task body();
    seq_write req_wr;
    begin
      `uvm_info(get_type_name(), $sformatf("Executing WRITE for %0d times...", count), UVM_LOW)
      repeat (count) begin
        `uvm_do(req_wr)
     end
    end
  endtask
endclass:seq_wr_rand

Simulation Output:
UVM_INFO seq_lib.sv(48) @ 0.0ns: uvm_test_top.env.my_agnt.sequencer@@seq_wr_rand [seq_wr_rand] addr_cfgd = x61
UVM_INFO seq_lib.sv(211) @ 0.0ns: uvm_test_top.env.my_agnt.sequencer@@seq_wr_rand [seq_wr_rand] Executing WRITE for 3 times…
UVM_INFO seq_lib.sv(180) @ 0.0ns: uvm_test_top.env.my_agnt.sequencer@@seq_wr_rand.req_wr [seq_write] Executing WRITE @ x014

2

In reply to santhg.90:

Because I do not see where you are performing the uvm_config_db set command it is impossible to answer your question.

3

In reply to chr_sue:
set config is done at ENV, & no error with it. When i run “seq_write” output is as expected which is x61. But with nested sequence “seq_wr_rand” it is not.

4

In reply to santhg.90:

If you are using `uvm_do(req_wr) super.body() will not be called automatically. You have to do this manually. Doing so should solve your issue.

5

In reply to santhg.90:
seq_wr_rand is getting the proper config_db value
You might be running this(seq_wr_rand) sequence with start method which calls pre_body and pet_body in turn.Thus no issue in uvm_config_db::get

whereas the sequence being called (seq_write) from it is not getting the config_db value and my test fails
The reason is 'uvm_do will not call pre_do and post_do method. Thus your base sequence is not performing the uvm_config_db::get properly.

Why don’t you perform uvm_config_db::get in sequencer and with the help of p_sequencer you can access cfg in any of the sequence.

6

In reply to Alay Patel:

The better solution is to make sure the settings of your base_sequence are executed.
By calling super.body() in seq_wr_rand you can reach this.
But you should decide for one coding style, using macros or not. Using start_item/finish_item will not have any issues as you are describing.
BTW pre_do/post_do are always executed in both options.

7

In reply to chr_sue:

Sorry it was a typo. I wanted to mention pre_body and post_body instead of pre_do and post_do respectively. I have corrected in my post.

Taking reference from UVM LRM:
Executing sub-sequences via uvm_do macros A sequence can also be indirectly started as a child in the body of a parent sequence. The child sequence’s start method is called indirectly by invoking any of the uvm_do
macros. In thise cases, start is called with call_pre_post set to 0, preventing the started
sequence’s pre_body and post_body methods from being called.

8

By using seq_wr_rand_obj.start(sequencer) method, i was able to achieve the required result…
Also in my current testbench i’m not having p_sequencer, so start method is easier option for me as of now.

Thanks chr_sue & Alay Patel for brief explanation on uvm_do macro.