We work in the Mixed Signal world and are often asked to verify the A/D and D/A functionality (connection, performance, functionality, etc.).
The main source of struggle is that Verilog-AMS, used for modeling the Analog blocks, doesn’t have the same possibility to be amended with a bind so that an interface can be connected to it.
Due to this limitation of Verilog-AMS, we often find ourselves including hierarchical paths in the BFMs that are preventing our VIP to be largely reusable. We haven’t found so far a lot of material on this, some mention a “gasket” as a way to interface with Verilog-AMS, but it does not abstract the path away, so you would still need to have a hierarchical path somewhere.
Any recommendation on how to deal with this problem?
When you are talking about AMS modules and bind you mean an isolated verification of these blocks in a bigger design?
Simulating a SoC with AMS modules is possible and you can switch between Spice and behavioral models. bind is not needed for such a scenario.
When you are talking about AMS modules and bind you mean an isolated verification of these blocks in a bigger design?
When we develop “system level verification” we not always have the luxury to just look at the boundaries of the DUT, but often we have to make sure that internal parts are behaving as expected when plugged together. I can give a straight example, we have a control loop that tries to adjust the gain of an amplifier to maintain it’s output to the ADC in a specific range. This loop is entails a piece of software, some digital control and an analog behavior, all contributing to achieve the goal of making the input of the ADC in within a specific range.
In this specific case, I would love to have a mechanism to “bind” my interface to the ADC model input, in a way that I can monitor it and even collect metrics on what has been covered. Simple PSL assertions here will not be useful since we know that input signal can be outside the range but it needs to go back in within a specific amount of time and the dynamic of the input signal is hard to capture with a simple assertion.
On the other hand we can build a model that “predicts” where the input signal needs to be at any given time and use that as a reference model.
In this real life example we are having difficulties to make this “connection” other than simply creating a hierarchical path access that is clearly difficult to abstract away if we want to build a verification IP that’s independent from the DUT.
Simulating a SoC with AMS modules is possible and you can switch between Spice and behavioral models. bind is not needed for such a scenario.
This is something that we do routinely and is not the problem we have. We typically use a verilog config module to specify which view to use for any given block of the netlist, so we have full control on whether we want only models, or a mixed of models and transistor level netlist, or backannotated gate-level netlists, etc.