In reply to sharatk:
This is a great question. It's also a good one for the SystemVerilog standard. The best improvement for both of them is making them even more stable by fixing all their bugs. The big problem with design by committee is that you can always get new energy from people to add in new features, but it's much more difficult to get the same kind of energy to fix bugs.
And then there's the issue of how one defines a bug. That's easy when a feature is completely unusable (see recent discussions of uvm_reg_fifo, but crosses the line into an enhancement when its missing a key feature to make it completely usable. (see discussions on umm_reg_map
Since the UVM is now just an IEEE document like the SystemVerilog standard, not actual code, my personal opinion is working on improving the standard to make sure it captures the intent of all features correctly the way people want it implemented.