Before UVM, How Systemverilog testbenches achieve features like UVM_config_db

UVM
1

Hi…
Can somebody explain Before UVM, How Systemverilog testbenches achieve features like UVM_config_db. I appreciate the help.

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In reply to prachi01:
I am guessing you have a hidden agenda behind this question: you want the functionality of the uvm_config_db in a non-UVM testbench. If that is the case, I suggest you just use the UVM class library for nothing else than the uvm_config_db. I tell people the same thing about the UVM reporting system. There really is no point in re-inventing everything in a testbench.

The uvm_config_db is not much more than an associative array indexed by a string. And there is an array for each type you want to store a value.

class config_db#(type T);
static T database[string]
static function void set(string name, T value);
   database[name] = value;
endfunction
static function bit get(string name, inout T value);
   if (database.exists(name) begin
     value = database[name];
     return 1;
   else 
     return 0;
endfunction
endclass
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In reply to dave_59:

Hi Dave,
Thanks for taking time to clarify. I’m curious to understand, what are systemverilog testbenches techniques used when there is no UVM methodology to achieve the same functionality of UVM_config_db. No hidden agenda as I work on UVM now :-)

Appreciate your clarification.

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In reply to prachi01:

There are as many good SystemVerilog testbench techniques as there are good verification engineers. The problem with that is trying to integrate the work between those engineers, or move engineers from project to project. The UVM may not always be the best technique for everything, but doing things in a consistent way is sometimes a benefit that overrides another way that might be just as good or slightly better.

I can see that you are just looking to get a better understanding of how the UVM works. I get anxious when people want to avoid using the UVM because they think it is too complex, but wind up implementing many of the same features of the UVM in a different way.

5

In reply to dave_59:

Hi Dave,
Thanks again for response. I appreciate UVM alot as it accelerates the verification. Would you able to throw some light on any of systemverilog techniques used in the past to achieve UVM_config_db functionality?

6

In reply to prachi01:
I though I already showed you that with the parameterized class above.

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In reply to dave_59:

Thanks Dave. I understood that in SV it can be realized with Static properties and functions.