Uvm: how to supress messages without severity from VHDL/Verilog DUT modules?

UVM
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When I’m starting the simulation, some DUT modules will start printing information without a severity level (e.g. by using $display). Most of it is completely useless (e.g. PLL got out of reset) and I would keep the transcript as clean as possible.

Is there a way I can do it from the testbench (without playing with the simulator options)?

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In reply to dipling:

You are out of luck when it comes to $display. You are going to have learn some some scripting tools like PERL or Python to filter your logs.

It is possible to override $display using the VPI and set up reporting system similarly to what the UVM report server does, but it would be far better to get everyone to use `uvm_info even from the DUT and even if they are not using a UVM testbench.

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In reply to dave_59:

Dave, thank you for the reply.

I already use some perl scripts for waiving warnings, they help reporting new/accepted warnings but the transcript still looks polluted. Also rewriting the $display calls is not feasible as many of them come from generated IPs.

Can you refer me to some documentation how to override $display using VPI?

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In reply to dipling: