UVM on the fly reset

Hi Everyone,

I am applying on the fly reset in my env. code is similar to this.



//code in Env

task main_phase(uvm_phase phase)
  if(on_fly_reset) begin
    #100000000;
    reset_dut();
  end
endtask
 
task reset_dut();
  reset_assert.start(null);
  vir_seqr.stop_sequnces();
  reset_deassert.start(null);
endtask    

//Code in test

task main_phase(uvm_phase phase);
  for(int i=0;i<10;i++) begin
    my_seq.start(env.vir_seqr);
  end
endtask

When on_fly_reset arg is enabled it asserts reset to dut,kill all sequences on vir seqr and de-asserts the reset. The problem is when reset is applied seq which is running is killed(this is fine) and the test is immediately starting the another seq on seqr.

I want my seqr to suspend till reset is de-asserted. Can someone provide me solution for this?

In reply to kranthi445:

The UVM provides the grab or lock mechanism for this kind of functionality. For more details look here:
https://verificationacademy.com/cookbook/sequences/lockgrab

In reply to chr_sue:

grab and lock need sequence pointer right?

In reply to kranthi445:

Which sequence pointer do you mean? But of course you have to grab a sequence and to start a new one.

In reply to chr_sue:

I am doing this in env component. I cant use vir_seqr.lock() right?

In reply to kranthi445:

You have to do this from the sequences. Review the corresponding code example (Interrupts - simple) from the Verification Academy.

In reply to chr_sue:

Any other way to do it? other than lock and grab.

Thanks
Kranthi

In reply to kranthi445:

There might be another solution, but grab/lock is only available with respect to sequences.
And this is the smartest way to do it.