UVM FATAL ERROR

UVM
1

neither the item’s sequencer nor dedicated sequencer has been supplied to start item in write_seq uvm fatal error

-Why these type of errors comes into picture?

2

In reply to NEHA JAIN:

Hi Neha,

Can you please share your code in which you are getting this error ?

Regards,
Chetan Shah

3

In reply to cashah85:

Hey, my problem is related to virtual sequencer, how it will handle the non-virtual sequencer.c
UVM fatal error is occurring for bad handle assignment.

//please any one can help me, how to assign handler to virtual sequencer through this method

** Fatal: (SIGSEGV) Bad handle or reference.

Time: 0 ns Iteration: 46 Process: /uvm_pkg::uvm_task_phase::execute/#FORK#138(#ublk#215181159#138)_ffd6674 File: C:/questasim_10.2c/win32/…/verilog_src/uvm-1.1d/src/base/uvm_common_phases.svh

Fatal error in Task and_vip_all_svh_unit/my_reset_test::run_phase at class/and_reset_test.sv line 42

-What i am doing is assigning the handler to virtual sequencer in test classes which are extends form test_base class. Like this–

//-----------------------Virtual sequencer---------------------------------------

//----------Virtual sequencer--------------------------------
class virtual_seqr extends uvm_sequencer#(and_transaction);

//References to non-virtual sequencer
//my_seqr real_seqr_inst;

 `uvm_component_utils(virtual_seqr)  //uvm factory....registration

function new(string name = "virtual_seqr", uvm_component parent=null);  //constructor
super.new(name,parent);
    endfunction

endclass: virtual_seqr
//-------------------------------end virtual sequencer----------------------------

//-------------------non virtual sequencer--------------------------------------------

class my_seqr extends uvm_sequencer#(and_transaction);

function new(string name = "my_seqr", uvm_component parent=null);  //constructor
super.new(name,parent);
    endfunction

    `uvm_component_utils(my_seqr)  //uvm factory....registration

endclass:my_seqr
//-------------------------------end non virtual sequencer------------------------------

//------------my_reset_test-------------------------------------------

class my_reset_test extends my_base_test;

`uvm_component_utils(my_reset_test) //uvm factory…registration

//------------------------------------------
// Methods
//------------------------------------------

// Standard UVM Methods:
//function new(string name = “my_reset_test”, uvm_component parent = null);
//function void build_phase(uvm_phase phase);
//task run_phase(uvm_phase phase);

function new(string name=“my_reset_test”, uvm_component parent=null); //constructor
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
super.build();
endfunction:build_phase

task run_phase(uvm_phase phase);
// uvm_info("test",$sformatf(" enter inside run_phase of PUT SEQUENCES ON SEQUENCER "),UVM_NONE); // uvm_info(“test”,$sformatf(" enter inside run_phase of my_reset_test "),UVM_NONE);

and_reset and_reset_inst = and_reset::type_id::create(“and_reset_inst”);

// We raise objection to keep the test from completing
phase.raise_objection(this, “Test Started”);

and_reset_inst.virtual_seqr_inst = env_inst.agent_inst.seqr; //fatal error is occurring beacsuse of this assignment

// start sequence put on the sequencer
and_reset_inst.start(null);
`uvm_info(“test”,$sformatf("and_reset seq starting "),UVM_NONE);

// #1000ns;
// uvm_report_info(“”,“Global Request”, UVM_LOW);
// global_stop_request();

// We drop objection to allow the test to complete
phase.drop_objection(this, “Test Finished”);
`uvm_info(“test”,$sformatf("and_reset seq ending "),UVM_NONE)

endtask :run_phase

function void end_of_elaboration();
print();
endfunction : end_of_elaboration

endclass :my_reset_test

//------------------------------------end my_reset_test------------------------------------

//-----------------------------------------agent class------------------------------------

//-----------------------agent-----------------------
// The agent contains sequencer, driver, and monitor (not included)
class my_agent extends uvm_component;
`uvm_component_utils(my_agent)

//*********************************************************
// Create Instance of analysis port
//*********************************************************
uvm_analysis_port #(and_transaction) ap;

//*********************************************************
// Create Instance of agent configuration
//*********************************************************
agent_config agent_config_inst;

//*********************************************************
// Create Instance of Sequencer
//*********************************************************
my_seqr seqr;

//*********************************************************
// Create Instance of Sequencer
//*********************************************************
// virtual_seqr virtual_seqr_inst;

//*********************************************************
// Create Instance of Driver
//*********************************************************
my_driver drv;

//*********************************************************
// Create Instance of Monitor
//*********************************************************
my_monitor monitor;

function new (string name, uvm_component parent);
super.new(name,parent);
endfunction

//*********************************************************
// Build Method
//*********************************************************

function void build_phase(uvm_phase phase);
super.build_phase(phase);

//*********************************************************
// Construct analysis port
//*********************************************************

uvm_report_info(“”,“Creating Agent Analaysis Port…”, UVM_LOW);
ap = new(“ap”, this);

//*********************************************************
// Construct agent configuration
//*********************************************************

uvm_report_info(“”,“Creating Agent Configuration…”, UVM_LOW);
agent_config_inst = agent_config::type_id::create( .name( “agent_config_inst” ), .parent( this ) );

//*********************************************************
// Check agent configuration = ACTIVE

// Construct Driver and Sequencer
//*********************************************************
if ( agent_config_inst.active == UVM_ACTIVE )
begin
uvm_report_info(“”,“Creating Driver and Sequencer…”, UVM_LOW);
drv = my_driver::type_id::create(“drv”, this);
seqr = my_seqr::type_id::create(“seqr”, this);
// virtual_seqr_inst = virtual_seqr::type_id::create(“virtual_seqr_inst”, this);
end

//*********************************************************
// Construct Monitor
// Agent Configuration = ACTIVE OR PASSIVE
//*********************************************************
uvm_report_info(“”,“Creating Monitor…”, UVM_LOW);
monitor = my_monitor::type_id::create( .name( “monitor”), .parent( this ) );
endfunction: build_phase

//endfunction : build_phase

//*********************************************************
// Connection Method
//*********************************************************
// In UVM connect phase, we connect the sequencer to the driver.

function void connect_phase(uvm_phase phase);

//*********************************************************
// Connecting Agent and Monitor(TLM port - port)
// analysis port[agent] <—> analysis port[monitor]
//********************************************************

uvm_report_info(“”,“Connecting Agent and Monitor…”, UVM_LOW);
ap = monitor.ap;

//*********************************************************
// Check agent configuration = ACTIVE &
// Connecting Driver and Sequencer (TLM port - export)
// seq_item_port[driver] <—> seq_item_export[sequencer]
//*********************************************************

if ( agent_config_inst.active == UVM_ACTIVE ) begin
uvm_report_info(“”,“Connecting Driver and Sequencer…”, UVM_LOW);
drv.seq_item_port.connect(seqr.seq_item_export);
//drv.seq_item_port.connect(virtual_seqr.seq_item_export);

end

endfunction :connect_phase

endclass

//--------------------------------------end agent_class------------------------------------------------------

4

In reply to NEHA JAIN:

Can you please elaborate what is the intent of this line?

and_reset_inst.virtual_seqr_inst = env_inst.agent_inst.seqr

Regards,
Vikas

5

In reply to NEHA JAIN:

In reply to cashah85:
and_reset_inst.virtual_seqr_inst = env_inst.agent_inst.seqr; //fatal error is occurring beacsuse of this assignment

Your problem is in this line wher you are connecting your local (non-virtual) sequencer to the virtual sequencer instance. This is not legal, because the virtual sequencer is never generating seq_items.
You have to implement a handle to your local sequencer in the virtual sequencer. Then you can connect it in this way.