HI ,
I need to check, if my DUT does the same no of transfers as configured in the register.
Current approach involve passive monitoring of the interface(to count the number of transactions performed by the DUT) and checking against the register which indicates the number of transfers that DUT is supposed to do, ( this uses backdoor access of some registers) when a DONE register bit is set.
Meanwhile, I have front door and back door to the same register (at the same time) by different components(by sequence, scoreboard).
• Front door access is by a sequence which polls for a DONE bit in CTRL1 register &
• Backdoor access is by scoreboard which polls for a sameDONE register.
To avoid simultaneous access of the reg model , is it a good idea to use event in the sequence, which tells when the sequence has finished the register access, so that scoreboard can access the same register and do a backdoor access to check.
Is there any better method to achieve this…