UVM Driver needs to do 100(MAX_TRANS) transactions in which the address needs to transfer every posedge clock cycle and the data needs to transfer every four cycles(MAX_WAIT). I tried the below sample code, but didn’t get it to work.
please help me in this
class seq_item extends uvm_sequence_item;
rand bit [31:0]data;
rand bit [31:0] addr;
endclass
class sequen extends uvm_sequence#(seq_item);
`uvm_object_utils(sequen)
function new(string name = "sequen");
super.new(name);
endfunction
req = seq_item::type_id::create("seqn");
wait_for_grant();
assert(req.randomize());
send_request(req);
wait_for_item_done();
get_response(rsp);
endclass
interface inter_mem;
logic data;
logic addr;
modport DUT_Memory (input data, input addr);
endinterface
`define MAX_WAIT 4
`define MAX_TRANS 100
class seq_driver extends uvm_driver#(sequen);
//int data[$];
bit [31:0] data_store[$];
static int unsigned i,j,count;
`uvm_component_utils(driver)
function new(string name=seq_driver, uvm_component parent=NULL);
super.new(name,parent);
endfunction
virtual inter_mem vif;
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual reg_if)::get(this," ", "inter_mem", vif))
`uvm_fatal("DRV","Could not get vif")
endfunction
virtual task run_phase(uvm_phase phase);
super.run_phase(phase);
fork
begin
repeat (`MAX_TRANS) begin
forever begin
sequen seq;
`uvm_info("DRV", $sformatf("Wait for item from sequencer"),UVM_LOW)
@(posedge clk);
seq_item_port.get_next_item(seq);
drive_item_addr(seq);
seq_item_port.item_done();
end
end
begin
repeat (`MAX_TRANS) begin
#`MAX_WAIT;
drive_item_addr(bit [31:0] data_store[j]);
j++;
end
end
join_none
wait fork;
end
endtask
virtual task drive_item_addr(sequen seq);
vif.DUT_Memory.addr= seq.addr;
data_store[i] = seq.data;
i++;
endtask
virtual task dirve_item_data(bit [31:0] data);
vif.DUT_Memory.data = data;
endtask
endclass