Hi,
I have a UVM tb and currently the agents are attached to the top level ports of the DUT using interfaces.
So far everything is good.
Now I would like to have a subIP verification using the top level testbench and I am writing an agent to “talk”
to the internal IP
Now I have two similar questions on that.
A) What is the best way to disable the subIP ports that are driven from the internal logic using interfaces that exist in the RTL
I mean I would need to disable the outputs of the RTL block that drive the inputs of the subIP that I am creating the agent for
B) To do the above but if I don’t have interfaces in the RTL and the structural connectivity is a standard verilog/systemverilog
Thanks
In reply to george7272:
You need to removed the internal logic so it can be driven by your testbench. Toy can do with with conditional compilation (`ifdef) or generate-if statements with parameters. Another posibbilty is using a configuration and replacing modules with stub modules. Without knowing more about your internal logic, it’s difficult to suggest the best solution.
In reply to dave_59:
Hi Dave
If I remove the internal logic that drives the block that I will be verifying using an agent
I would implement it let’s say with compiling a stub module. Usually a stub module module
has all outputs as 0 or 1 and it depends the logic the stub module drive in order the interface to be considered inactive.
If my uvm driver is using the interface that connects the stub module and the logic under test then those 0 or 1 that are coming out from the stub module will conflict with the uvm driver/interface.
In theory the stub module should be driving the outputs with a weak 0 or 1 in order the interface to override those values
Would that be a good approach?
Is there another way without using a stub module but the real driving logic but the interface to override the driving values?
Also another solution that the RTL does not use interfaces for connecting modules ?
Thanks