class user_class extends uvm_sequence_item;
rand int thread_id;
rand int Var1;
...
endclass : user_class
class AA extends uvm_sequence_item;
rand int core_id;
rand user_class u_obj;
constraint c_set_core_thread_ids {u_obj.thread_id == core_id;}
endclass : AA
all my sequence/drivers are using class AA as the default sequence item.
in my sequence I have this:
int pid=1;
`uvm_do_with(req, {core_id==pid;});
First error I ran into was null obj deference:
Error-[NOA] Null object access
test_seq.sv, 147
The object at dereference depth 2 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
I fixed this after adding new() call for u_obj in class AA:
class AA extends uvm_sequence_item;
rand int core_id;
rand user_class u_obj = new();
constraint c_set_core_thread_ids {u_obj.thread_id == core_id;}
endclass : AA
Now after this i am running into constraint solver failure on thread_id rand variable.
=======================================================
Solver failed when solving following set of constraints
integer user_obj.thread_id = 0;
integer pid = 1;
rand integer core_id; // rand_mode = ON
constraint c_set_core_thread_ids // (from this) (constraint_mode = ON) (class_AA.sv:63)
{
(user_obj.thread_id == core_id);
}
constraint WITH_CONSTRAINT // (from this) (constraint_mode = ON) (test_seq.sv:146)
{
(core_id == pid);
}
=======================================================
It looks like simulator is considering user_class thread_id as a non-rand variable. At least i am not able to hierarchically set constraints on thread_id rand variable from top level sequence.
Any help in getting around this is appreciated.