UVM Connect Analysis connect SV -> SC

UVM
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1

Hi,

I am struggling right now with the problem to connect an SV analysis_port to SystemC using UVM Connect. So far, the following works:

  • tlm_analysis_port (SC) to uvm_analysis_imp (SV) using uvmc_tlm1::connect on SV (see example sv2sc2sv),
  • uvm_tlm_b_initiator_socket (SV) to simple_target_socket (SC).

I have made the SC class inherit from tlm_analysis_if and connect it. It does not work. I have used sc_export<tlm_analysis_if … It does not work. I used uvmc_tlm1::connect and uvmc_tlm::connect. The uvmc_tlm1 does not complain, but won’t work (SV → SC). The other command uvmc_tlm::connect complains at run-time that the type assignments (actual to formal) are incorrect. It complains that uvm_analysis_port is not of type uvm_base_port etc. According to the manual, analysis connections should be made via uvmc_tlm, but only uvmc_tlm1 works (in one direction, as used in the sv2sc2sv example). I have tried to use the tlm_analysis_fifo on the SC side, but uvmc_connect (SC) complains about multiple candidates (uvmc_connect for non/blocking put/get interfaces …).

I am using QuestaSim-64 10.2c_6, UVMC 2.3 and the UVM-1.1d that came with QuestaSim. UVM-1.2 did not compile with my QuestaSim (some SV syntax error). I have tried two combinations: UVMC lib + prebuilt UVM lib, UVMC + recompiled UVM lib (in the same installation directory). No differences.

Does UVMC actually support SV → SC via analysis ports? I see no example included in the documentation. If so, I could maybe provide a minimal working example.

Thanks in advance!
BR, Dominik

2

Here is the bugfix to UVMC 2.3.

In uvmc-2.3/src/connect/sc/uvmc_ports.h

// ANALYSIS (WRITE)

template &lt;class T,
          class CVRT=uvmc_converter&lt;T> >
class uvmc_analysis_port
    : virtual public uvmc_tlm1_port_proxy&lt;T,T,CVRT,CVRT>,
      virtual public tlm_analysis_port&lt;T>
{
  public:
  typedef tlm_analysis_if&lt;T> if_type;
  typedef tlm_analysis_port&lt;T> port_type;
  typedef uvmc_tlm1_port_proxy&lt;T,T,CVRT,CVRT> proxy_type;

  uvmc_analysis_port(const string name,
                     const string lookup,
                     uvmc_packer *packer=NULL) :
       proxy_type(name,lookup,TLM_ANALYSIS_MASK,packer),
       port_type((string("UVMC_PORT_FOR_") +
                         uvmc_legal_path(name)).c_str()) {
    sc_core::sc_get_curr_simcontext()->hierarchy_pop();
  }

  virtual const char *kind() const {·
    return "uvmc_analysis_port&lt;>";·
  }
  virtual const char *name() const {·
    return proxy_type::name();
  }
  
  // BUGFIX START
  virtual void write(const T &t) { port_type::write(t); }
  // BUGFIX END

  private:
  uvmc_analysis_port( );
};

The issue is that uvmc_tlm1_port_proxy calls write, but won’t be forwarded to write of tlm_analysis_port. This needs to be done explicitly inside uvmc_analysis_port. Note that the other uvmc_*_port classes do exactly that.

Maybe in the uvmc_tlm1_port_proxy class, the empty virtual function write could report an error:

virtual void write    (const T1 &t) {
    printf("ERROR: write() not overloaded, at %s, kind %s\n", name(), kind());
  }

P.S.: The forum has an issue with < inside code tags, interpreting it as an opening to an HTML tag.