In reply to vlsique:
There are a number of issues accessing a variable in one class object from another class object that do not exist in a traditional non-class based (Verilog) testbench.
Unless the object containing the variable is on a direct downward path from where it is being accessed, you need to know the type of the containing object in order to reference the variable. This usually creates a circular type dependency which may be impossible to resolve if the two class types are defined in separate packages.
Class objects are dynamically constructed and have no fixed path structure. The UVM builds a parent-child relationship for classes derived from uvm_component which gives you a path you can use. But it's very difficult to get paths to or from other objects like uvm_sequence_item.
And in any methodology, the use of hierarchical path makes your code difficult to maintain and re-use.