Hi all,
When compiling some UVM project, how do you manage to compile all files without having any dependencies (transaction, driver, scoreboard, sequencer, tests, etc… ) error appearing?
I would like to have each of them in separate files.
Is there any standard processing?
Thanks!
In reply to Andrei_:
You can always put each class declaration in separate file, and use `include “classname.svh” to include them into a package. We recommend putting all classes for a each agent in an individual package, all your higher level testbench components in another package (scoreboards, env, coverage collectors), and your tests in one or more other packages. Putting your classes into separate packages will force some level of dependencies, but within a package, you can be more lenient with the order of your classes by using a forward typedef (See section 8.27 Typedef class in the 1800-2012 SystemVerilog LRM).
I would also recommend that you keep the use of forward typedefs to a minimum and `include your files in the proper order. It will be more manageable in the long run.