Uvm check doubt

Hi,

I have a payload which is 32 bits where i have different attributes like some tags, ids and length. The length is 4

i am trying to write a check where i want to see of one of the attributes is set to one , when it is set to one, no other attributes should be set to one.

example:

line 1- if (packet.payload[packet.length-1][3] == 1)
line 2- if (packet.payload[packet.length-1-2] & 'hae) != 0
line 3- `uvm_error()

for line 1- does this seem correct since I am trying to access the index of a particular attribute and checking if its set to 1, but what about the length in that case?

In reply to pkc431:

It would help if you showed a little more code for this SystemVerilog question. Here is my guess as to the surrounding code, and solution. Wrap this up in a module and give it a try.

typedef bit [15:0] payload_t;
class Packet;
  payload_t length, payload[], mask = 'b0000_1000;
endclass

function bit check(Packet packet);
  if (packet.payload[packet.length] & mask) begin
    if (packet.payload[packet.length] & ~mask) begin
      $error("BAD BITS");
    end
  end
endfunction